44 lines
929 B
Verilog
44 lines
929 B
Verilog
`default_nettype none
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module top(i_clk, o_led, lcol1);
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parameter WIDTH = 22;
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input wire i_clk;
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output reg [7:0] o_led;
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output wire lcol1;
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wire clk_12MHz;
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clk_gen clk_gen_0 (/*autoinst*/
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// Outputs
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.o_clk (clk_12MHz),
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// Inputs
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.i_clk (i_clk));
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reg [WIDTH-1:0] counter;
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reg [7:0] obuf; // output buffer, take into account the icefun use active low LED
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reg strobe;
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initial begin
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obuf = 8'h1;
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{strobe, counter} = 0;
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end
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always @(posedge clk_12MHz)
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{strobe, counter} <= counter + 1'b1;
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// shifting bit
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always @(posedge clk_12MHz)
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if (strobe)
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obuf <= {obuf[6:0], obuf[7]}; // left shift
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// obuf <= {obuf[0], obuf[7:1]}; // right shift
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always @(*)
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o_led = ~obuf;
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assign lcol1 = 1'b0;
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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