`default_nettype  none

module top(i_clk, o_led, lcol1);
   parameter WIDTH = 22;
   input wire i_clk;
   output reg [7:0] o_led;
   output wire lcol1;

   wire clk_12MHz;

   clk_gen clk_gen_0 (/*autoinst*/
      // Outputs
      .o_clk                 (clk_12MHz),
      // Inputs
      .i_clk                 (i_clk));

   reg [WIDTH-1:0] counter;
   reg [7:0] obuf; // output buffer, take into account the icefun use active low LED
   reg strobe;

   initial begin
      obuf = 8'h1;
      {strobe, counter} = 0;
   end

   always @(posedge clk_12MHz)
      {strobe, counter} <= counter + 1'b1;

   // shifting bit
   always @(posedge clk_12MHz)
      if (strobe)
         obuf <= {obuf[6:0], obuf[7]}; // left shift
         // obuf <= {obuf[0], obuf[7:1]}; // right shift

   always @(*)
      o_led = ~obuf;

   assign lcol1 = 1'b0;
endmodule

// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: