71 lines
1.5 KiB
Verilog
71 lines
1.5 KiB
Verilog
`default_nettype none
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module top(i_clk,
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i_cyc, i_stb, i_we, i_addr, i_data,
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o_stall, o_ack, o_data,
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o_led, o_led_row_0);
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input wire i_clk;
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//
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// Our wishbone bus interface
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input wire i_cyc, i_stb, i_we;
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input wire i_addr;
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input wire [31:0] i_data;
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//
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output wire o_stall;
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output reg o_ack;
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output wire [31:0] o_data;
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//
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// The output LED
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output wire o_led_row_0;
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output reg [5:0] o_led;
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wire busy;
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reg [3:0] state;
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initial state = 0;
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always @(posedge i_clk) begin
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if ((i_stb)&&(i_we)&&(!o_stall))
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state <= 4'h1;
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else if (state >= 4'd11)
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state <= 4'h0;
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else if (state != 0)
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state <= state + 1'b1;
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end
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always @(posedge i_clk) begin
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case(state)
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4'h1: o_led <= 6'b00_0001;
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4'h2: o_led <= 6'b00_0010;
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4'h3: o_led <= 6'b00_0100;
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4'h4: o_led <= 6'b00_1000;
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4'h5: o_led <= 6'b01_0000;
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4'h6: o_led <= 6'b10_0000;
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4'h7: o_led <= 6'b01_0000;
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4'h8: o_led <= 6'b00_1000;
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4'h9: o_led <= 6'b00_0100;
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4'ha: o_led <= 6'b00_0010;
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4'hb: o_led <= 6'b00_0001;
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default: o_led <= 6'b00_0000;
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endcase
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end
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assign busy = (state != 0);
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initial o_ack = 1'b0;
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always @(posedge i_clk)
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o_ack <= (i_stb)&&(!o_stall);
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assign o_stall = (busy)&&(i_we);
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assign o_data = { 28'h0, state };
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assign o_led_row_0 = 0;
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// Verilator lint_off UNUSED
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wire [33:0] unused;
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assign unused = { i_cyc, i_addr, i_data };
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// Verilator lint_on UNUSED
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//
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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