use only top bits of the data to display

tdc/rtl/clk_gen.v

@@ -2,17 +2,29 @@
 // dummy clock generator, should be replaced by a PLL clock gen eventually
 module clk_gen #(parameter DIVISION=22)(
    input wire i_clk,
-   output wire o_clk
+   output wire o_clk_100MHz,
+   output wire o_div_clk
 );
 
-reg [DIVISION-1:0] counter = 0;
-
-always @(posedge i_clk) begin
+/* verilator lint_off PINCONNECTEMPTY */
+/* verilator lint_off PINMISSING */
+   reg [DIVISION-1:0] counter = 0;
+`ifdef VERILATOR
+   always @(posedge i_clk) begin
       counter <= counter + 1;
-end
+   end
 
-assign o_clk = counter[DIVISION-1];
+   assign o_clk_100MHz = i_clk;
+`else
+   pll_100MHz pll0(.i_clk(i_clk), .o_clk_100MHz(o_clk_100MHz), .o_pll_locked());
+   always @(posedge o_clk_100MHz) begin
+      counter <= counter + 1;
+   end
+`endif
 
+   assign o_div_clk = counter[DIVISION-1];
+/* verilator lint_on PINCONNECTEMPTY */
+/* verilator lint_on PINMISSING */
 endmodule
 // Local Variables:
 // verilog-library-directories:(".." "./rtl" ".")

tdc/rtl/debounce.v

@@ -0,0 +1,115 @@
+// Listing 5.6
+module debounce
+   (
+    input wire clk, reset,
+    input wire sw,
+    output reg db
+   );
+
+   // symbolic state declaration
+   localparam  [2:0]
+               zero    = 3'b000,
+               wait1_1 = 3'b001,
+               wait1_2 = 3'b010,
+               wait1_3 = 3'b011,
+               one     = 3'b100,
+               wait0_1 = 3'b101,
+               wait0_2 = 3'b110,
+               wait0_3 = 3'b111;
+
+   // number of counter bits (2^N * 10ns = 10ms tick)
+   localparam N =20;
+
+   // signal declaration
+   reg [N-1:0] q_reg;
+   wire [N-1:0] q_next;
+   wire m_tick;
+   reg [2:0] state_reg, state_next;
+
+   // body
+
+   //=============================================
+   // counter to generate 10 ms tick
+   //=============================================
+   always @(posedge clk)
+      q_reg <= q_next;
+   // next-state logic
+   assign q_next = q_reg + 1;
+   // output tick
+   assign m_tick = (q_reg==0) ? 1'b1 : 1'b0;
+
+   //=============================================
+   // debouncing FSM
+   //=============================================
+   // state register
+    always @(posedge clk, posedge reset)
+       if (reset)
+          state_reg <= zero;
+       else
+          state_reg <= state_next;
+
+   // next-state logic and output logic
+   always @*
+   begin
+      state_next = state_reg;  // default state: the same
+      db = 1'b0;               // default output: 0
+      case (state_reg)
+         zero:
+            if (sw)
+               state_next = wait1_1;
+         wait1_1:
+            if (~sw)
+               state_next = zero;
+            else
+               if (m_tick)
+                  state_next = wait1_2;
+         wait1_2:
+            if (~sw)
+               state_next = zero;
+            else
+               if (m_tick)
+                  state_next = wait1_3;
+         wait1_3:
+            if (~sw)
+               state_next = zero;
+            else
+               if (m_tick)
+                  state_next = one;
+         one:
+            begin
+              db = 1'b1;
+              if (~sw)
+                 state_next = wait0_1;
+            end
+         wait0_1:
+            begin
+               db = 1'b1;
+               if (sw)
+                  state_next = one;
+               else
+                 if (m_tick)
+                    state_next = wait0_2;
+            end
+         wait0_2:
+            begin
+               db = 1'b1;
+               if (sw)
+                  state_next = one;
+               else
+                 if (m_tick)
+                    state_next = wait0_3;
+            end
+         wait0_3:
+            begin
+               db = 1'b1;
+               if (sw)
+                  state_next = one;
+               else
+                 if (m_tick)
+                    state_next = zero;
+            end
+         default: state_next = zero;
+      endcase
+   end
+
+endmodule

tdc/rtl/pll_100MHz.v

@@ -0,0 +1,40 @@
+/**
+* PLL configuration
+*
+* This Verilog module was generated automatically
+* using the icepll tool from the IceStorm project.
+* Use at your own risk.
+*
+* Given input frequency:        12.000 MHz
+* Requested output frequency:  100.000 MHz
+* Achieved output frequency:   100.500 MHz
+*/
+// this module is skipped by verilator
+`ifdef VERILATOR
+`else
+   module pll_100MHz(
+      input  i_clk,
+      output o_clk_100MHz,
+      output o_pll_locked
+   );
+
+   wire clk_int;
+   SB_PLL40_CORE #(
+      .FEEDBACK_PATH("SIMPLE"),
+      .DIVR(4'b0000),		// DIVR =  0
+      .DIVF(7'b1000010),	// DIVF = 66
+      .DIVQ(3'b011),		// DIVQ =  3
+      .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+   ) uut (
+      .LOCK(o_pll_locked),
+      .RESETB(1'b1),
+      .BYPASS(1'b0),
+      .REFERENCECLK(i_clk),
+      .PLLOUTCORE(clk_int)
+   );
+
+   SB_GB sbGlobalBuffer_inst( .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_int),
+      .GLOBAL_BUFFER_OUTPUT(o_clk_100MHz));
+
+endmodule
+`endif

tdc/rtl/tdc.v

@@ -12,6 +12,21 @@ module tdc #(parameter COUNTER_WIDTH=16)(
 reg [COUNTER_WIDTH-1:0] counter;
 assign o_data = counter;
 
+reg db_start, db_stop;
+debounce db1 (
+   // Outputs
+   .db                       (db_start),
+   // Inputs
+   .clk                      (i_clk),
+   .reset                    (i_reset),
+   .sw                       (i_start));
+debounce db2 (
+   // Outputs
+   .db                       (db_stop),
+   // Inputs
+   .clk                      (i_clk),
+   .reset                    (i_reset),
+   .sw                       (i_stop));
 // states
 localparam state_idle = 2'b00;
 localparam state_started = 2'b01;
@@ -20,7 +35,7 @@ localparam state_stopped = 2'b11;
 reg [1:0] current_state, next_state;
 
 // ensure that state changes each clock
-always @(posedge i_clk) begin
+always @(posedge i_clk, posedge i_reset) begin
    if (i_reset) begin
       current_state <= state_idle;
    end else begin
@@ -33,19 +48,19 @@ end
 always @(*) begin
    case (current_state)
       state_idle: begin
-         if (i_start && (~i_stop))
+         if (db_start && (~db_stop))
             next_state <= state_started;
          else
             next_state <= state_idle;
       end
       state_started: begin
-         if (~i_start && (~i_stop))
+         if (~db_start && (~db_stop))
             next_state <= state_running;
          else
             next_state <= state_started;
       end
       state_running: begin
-         if (~i_start && (i_stop))
+         if (~db_start && (db_stop))
             next_state <= state_stopped;
          else
             next_state <= state_running;

tdc/rtl/top.v

@@ -10,30 +10,35 @@ module top #(parameter WIDTH=24)(
    output wire [5:0] o_dataN,
    output wire o_led_row_0
 );
-   wire clk_3Hz;
+   wire clk_1Hz; // 1.4 Hz actually
+   wire clk_100MHz;
    reg buf_led = 0;
    wire buf_ready;
-   wire [5:0] buf_data;
+   /* verilator lint_off UNUSED */
+   parameter TDC_COUNTER_WIDTH = 28;
+   wire [TDC_COUNTER_WIDTH-1:0] buf_data;
    assign o_readyN = ~buf_ready;
-   assign o_dataN = ~buf_data;
+   assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
+   /* verilator lint_on UNUSED */
 
-   clk_gen #(.DIVISION(22)) clk_gen0 (/*autoinst*/
-                      // Outputs
-                      .o_clk            (clk_3Hz),
-                      // Inputs
+/* verilator lint_off PINMISSING */
+   clk_gen #(.DIVISION(26)) clk_gen0 (
+                      .o_div_clk        (clk_1Hz),
+                      .o_clk_100MHz (clk_100MHz),
                       .i_clk            (i_clk));
+/* verilator lint_on PINMISSING */
 
-   tdc #(.COUNTER_WIDTH(6)) tdc0 (/*autoinst*/
+   tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
             // Outputs
             .o_ready                    (buf_ready),
             .o_data                     (buf_data),
             // Inputs
-            .i_clk                      (clk_3Hz),
+            .i_clk                      (clk_100MHz),
             .i_start                    (~i_startN),
             .i_stop                     (~i_stopN),
             .i_reset                   (~i_resetN));
 
-   always @(posedge clk_3Hz) begin
+   always @(posedge clk_1Hz) begin
       buf_led <= ~buf_led;
    end
 

tdc/sim/top.cc

@@ -46,9 +46,12 @@ int main(int argc, char **argv) {
    for (int k = 0; k < 3; k++) 
       tick(++tickcount, tb, tfp);
 
+   for (int i = 0; i < 1000; i++) {
       tb->i_startN = 0;
       tick(++tickcount, tb, tfp);
       tb->i_startN = 1;
+      tick(++tickcount, tb, tfp);
+   }
 
    for (int k = 0; k < 15; k++) 
       tick(++tickcount, tb, tfp);