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base: nam:3a9c0343c121b48517bc59fc3a50db4fef90cb9f
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nam:master nam:naive_3Hz_stopwatch nam:tut4-with-strobe
nam:tdc_manual_start_stop_uart_tx nam:tdc_uart_tx
..
compare: nam:tut4-with-strobe
Branches Tags
nam:master nam:naive_3Hz_stopwatch nam:tut4-with-strobe
nam:tdc_manual_start_stop_uart_tx nam:tdc_uart_tx

1 Commits
3a9c0343c1 ... tut4-with-

Author SHA1 Message Date
Nam Tran
556a79e705 tut4 with strobe, stuck at the last transition 2020-10-25 17:55:16 -05:00
2 changed files with 66 additions and 78 deletions
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20
fsm-tut4/rtl/clk_gen.v
View File

@@ -5,25 +5,7 @@ module clk_gen(
output wire o_clk output wire o_clk
); );
// assign o_clk = i_clk; assign o_clk = i_clk;
reg [31:0] counter;
reg buf_clk;
parameter CLK_RATE_HZ = 12_000_000;
initial begin
counter = 0;
buf_clk = 0;
end
assign o_clk = buf_clk;
always @(posedge i_clk) begin
if (counter >= CLK_RATE_HZ/2 - 1) begin
counter <= 0;
buf_clk <= ~buf_clk;
end
else
counter <= counter + 1;
end
endmodule endmodule
// Local Variables: // Local Variables:

124
fsm-tut4/rtl/top.v
View File

@@ -8,17 +8,18 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
input wire i_request; input wire i_request;
output wire o_busy; output wire o_busy;
wire clk_1Hz; wire clk_12MHz;
clk_gen clk_gen_0 (/*autoinst*/ clk_gen clk_gen_0 (/*autoinst*/
// Outputs // Outputs
.o_clk (clk_1Hz), .o_clk (clk_12MHz),
// Inputs // Inputs
.i_clk (i_clk)); .i_clk (i_clk));
reg [WIDTH-1:0] counter; reg [WIDTH-1:0] counter;
reg [3:0] state; reg [3:0] state;
reg [5:0] led_buf; // output buffer, take into account the icefun use active low LED reg [5:0] led_buf; // output buffer, take into account the icefun use active low LED
reg strobe;
reg busy_buf; reg busy_buf;
wire req_buf; wire req_buf;
@@ -29,90 +30,95 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
initial begin initial begin
led_buf = 6'h0; led_buf = 6'h0;
counter = 0; {strobe, counter} = 0;
// counter = 0;
state = 0; state = 0;
busy_buf = 0; busy_buf = 0;
end end
always @(posedge clk_1Hz) begin always @(posedge clk_12MHz) begin
if (!busy_buf && req_buf) if (!busy_buf && req_buf)
busy_buf <= 1; busy_buf <= 1;
else else
busy_buf <= (state != 4'h0); busy_buf <= (state != 4'h0);
end end
// counter and strobe run only during busy signal is High // counter and strobe run only during busy signal is High
always @(posedge clk_1Hz) begin always @(posedge clk_12MHz) begin
if (busy_buf) if (busy_buf)
counter <= counter + 1'b1; // counter <= counter + 1'b1;
{strobe, counter} <= counter + 1'b1;
else else
counter <= 0; {strobe, counter} <= 0;
// counter <= 0;
end end
always @(posedge clk_1Hz) begin // state change once strobe starts
always @(posedge clk_12MHz) begin
if (!busy_buf && req_buf) if (!busy_buf && req_buf)
state <= 4'h1; state <= 4'h1;
else if (state >= 4'hB) else if (state >= 4'hB && strobe)
state <= 4'h0; state <= 4'h0;
else if (state != 0) else if (state != 0 && strobe)
state <= state + 1'b1; state <= state + 1'b1;
end end
// fsm for led_buf // fsm for led_buf
always @(posedge clk_1Hz) begin always @(posedge clk_12MHz) begin
case (state) if (strobe)
4'h1: led_buf <= 6'b00_0001; case (state)
4'h2: led_buf <= 6'b00_0010; 4'h1: led_buf <= 6'b00_0001;
4'h3: led_buf <= 6'b00_0100; 4'h2: led_buf <= 6'b00_0010;
4'h4: led_buf <= 6'b00_1000; 4'h3: led_buf <= 6'b00_0100;
4'h5: led_buf <= 6'b01_0000; 4'h4: led_buf <= 6'b00_1000;
4'h6: led_buf <= 6'b10_0000; 4'h5: led_buf <= 6'b01_0000;
4'h7: led_buf <= 6'b01_0000; 4'h6: led_buf <= 6'b10_0000;
4'h8: led_buf <= 6'b00_1000; 4'h7: led_buf <= 6'b01_0000;
4'h9: led_buf <= 6'b00_0100; 4'h8: led_buf <= 6'b00_1000;
4'ha: led_buf <= 6'b00_0010; 4'h9: led_buf <= 6'b00_0100;
4'hb: led_buf <= 6'b00_0001; 4'ha: led_buf <= 6'b00_0010;
default: led_buf <= 6'b00_0000; 4'hb: led_buf <= 6'b00_0001;
endcase default: led_buf <= 6'b00_0000;
endcase
end end
`ifdef FORMAL `ifdef FORMAL
// state should never go beyond 13 // state should never go beyond 13
always @(*) always @(*)
assert(state <= 4'hd); assert(state <= 4'hd);
// I prefix all of the registers (or wires) I use in formal // I prefix all of the registers (or wires) I use in formal
// verification with f_, to distinguish them from the rest of the // verification with f_, to distinguish them from the rest of the
// project. // project.
reg f_valid_output; reg f_valid_output;
always @(*) always @(*)
begin begin
// Determining if the output is valid or not is a rather // Determining if the output is valid or not is a rather
// complex task--unusual for a typical assertion. Here, we'll // complex task--unusual for a typical assertion. Here, we'll
// use f_valid_output and a series of _blocking_ statements // use f_valid_output and a series of _blocking_ statements
// to determine if the output is one of our valid outputs. // to determine if the output is one of our valid outputs.
f_valid_output = 0; f_valid_output = 0;
case(led_buf) case(led_buf)
8'h01: f_valid_output = 1'b1; 8'h01: f_valid_output = 1'b1;
8'h02: f_valid_output = 1'b1; 8'h02: f_valid_output = 1'b1;
8'h04: f_valid_output = 1'b1; 8'h04: f_valid_output = 1'b1;
8'h08: f_valid_output = 1'b1; 8'h08: f_valid_output = 1'b1;
8'h10: f_valid_output = 1'b1; 8'h10: f_valid_output = 1'b1;
8'h20: f_valid_output = 1'b1; 8'h20: f_valid_output = 1'b1;
8'h40: f_valid_output = 1'b1; 8'h40: f_valid_output = 1'b1;
8'h80: f_valid_output = 1'b1; 8'h80: f_valid_output = 1'b1;
endcase endcase
assert(f_valid_output); assert(f_valid_output);
// SV supports a $onehot function which we could've also used // SV supports a $onehot function which we could've also used
// depending upon your version of Yosys. This function will // depending upon your version of Yosys. This function will
// be true if one, and only one, bit in the argument is true. // be true if one, and only one, bit in the argument is true.
// Hence we might have said // Hence we might have said
// assert($onehot(o_led)); // assert($onehot(o_led));
// and avoided this case statement entirely. // and avoided this case statement entirely.
end end
`endif `endif
endmodule endmodule