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tut4 with strobe, stuck at the last transition

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Nam Tran
2020-10-25 17:55:16 -05:00
parent 6096187250
commit 556a79e705
1 changed files with 10 additions and 10 deletions
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20
fsm-tut4/rtl/top.v
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@@ -19,7 +19,7 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
reg [WIDTH-1:0] counter;
reg [3:0] state;
reg [5:0] led_buf; // output buffer, take into account the icefun use active low LED
// reg strobe;
reg strobe;
reg busy_buf;
wire req_buf;
@@ -30,8 +30,8 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
initial begin
led_buf = 6'h0;
// {strobe, counter} = 0;
counter = 0;
{strobe, counter} = 0;
// counter = 0;
state = 0;
busy_buf = 0;
end
@@ -45,26 +45,26 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
// counter and strobe run only during busy signal is High
always @(posedge clk_12MHz) begin
if (busy_buf)
counter <= counter + 1'b1;
// {strobe, counter} <= counter + 1'b1;
// counter <= counter + 1'b1;
{strobe, counter} <= counter + 1'b1;
else
// {strobe, counter} <= 0;
counter <= 0;
{strobe, counter} <= 0;
// counter <= 0;
end
// state change once strobe starts
always @(posedge clk_12MHz) begin
if (!busy_buf && req_buf)
state <= 4'h1;
else if (state >= 4'hB)
else if (state >= 4'hB && strobe)
state <= 4'h0;
else if (state != 0)
else if (state != 0 && strobe)
state <= state + 1'b1;
end
// fsm for led_buf
always @(posedge clk_12MHz) begin
// if (strobe)
if (strobe)
case (state)
4'h1: led_buf <= 6'b00_0001;
4'h2: led_buf <= 6'b00_0010;