tut4 with strobe, stuck at the last transition

fsm-tut4/rtl/clk_gen.v

@@ -5,25 +5,7 @@ module clk_gen(
    output wire o_clk
 );
 
-// assign o_clk = i_clk;
+assign o_clk = i_clk;
-reg [31:0] counter;
-reg buf_clk;
-parameter CLK_RATE_HZ = 12_000_000;
-
-initial  begin
-   counter = 0;
-   buf_clk = 0;
-end
-assign o_clk = buf_clk;
-
-always @(posedge i_clk) begin
-   if (counter >= CLK_RATE_HZ/2 - 1) begin
-      counter <= 0;
-      buf_clk <= ~buf_clk; 
-   end
-   else
-      counter <= counter + 1;
-end
 
 endmodule
 // Local Variables:

fsm-tut4/rtl/top.v

@@ -8,17 +8,18 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
    input wire i_request;
    output wire o_busy;
 
-   wire clk_1Hz;
+   wire clk_12MHz;
 
    clk_gen clk_gen_0 (/*autoinst*/
       // Outputs
-      .o_clk                 (clk_1Hz),
+      .o_clk                 (clk_12MHz),
       // Inputs
       .i_clk                 (i_clk));
 
    reg [WIDTH-1:0] counter;
    reg [3:0] state;
    reg [5:0] led_buf; // output buffer, take into account the icefun use active low LED
+   reg strobe;
    reg busy_buf;
    wire req_buf;
 
@@ -29,36 +30,41 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
 
    initial begin
       led_buf = 6'h0;
-      counter = 0;
+      {strobe, counter} = 0;
+      // counter = 0;
       state = 0;
       busy_buf = 0;
    end
 
-   always @(posedge clk_1Hz) begin
+   always @(posedge clk_12MHz) begin
       if (!busy_buf && req_buf)
          busy_buf <= 1;
       else
          busy_buf <= (state != 4'h0);
    end
    // counter and strobe run only during busy signal is High
-   always @(posedge clk_1Hz) begin
+   always @(posedge clk_12MHz) begin
       if (busy_buf)
-         counter <= counter + 1'b1;
+         // counter <= counter + 1'b1;
+         {strobe, counter} <= counter + 1'b1;
       else
-         counter <= 0;
+         {strobe, counter} <= 0;
+         // counter <= 0;
    end
 
-   always @(posedge clk_1Hz) begin
+   // state change once strobe starts
+   always @(posedge clk_12MHz) begin
       if (!busy_buf && req_buf)
          state <= 4'h1;
-      else if (state >= 4'hB)
+      else if (state >= 4'hB && strobe)
          state <= 4'h0;
-      else if (state != 0)
+      else if (state != 0 && strobe)
          state <= state + 1'b1;
    end
 
    // fsm for led_buf
-   always @(posedge clk_1Hz) begin
+   always @(posedge clk_12MHz) begin
+      if (strobe)
          case (state)
             4'h1: led_buf <= 6'b00_0001;
             4'h2: led_buf <= 6'b00_0010;
@@ -75,7 +81,7 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
          endcase
    end
 
-   `ifdef	FORMAL
+`ifdef	FORMAL
    // state should never go beyond 13
 	always @(*)
 		assert(state <= 4'hd);
@@ -112,7 +118,7 @@ module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
       // assert($onehot(o_led));
       // and avoided this case statement entirely.
    end
-   `endif
+`endif
 
 endmodule