working stop watch

tdc/rtl/clk_gen.v

@@ -1,11 +1,17 @@
 `default_nettype none
 // dummy clock generator, should be replaced by a PLL clock gen eventually
-module clk_gen(
+module clk_gen #(parameter DIVISION=22)(
    input wire i_clk,
    output wire o_clk
 );
 
-assign o_clk = i_clk;
+reg [DIVISION-1:0] counter = 0;
+
+always @(posedge i_clk) begin
+   counter <= counter + 1;
+end
+
+assign o_clk = counter[DIVISION-1];
 
 endmodule
 // Local Variables: