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working stop watch

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Nam Tran
2020-10-26 17:35:52 -05:00
parent 4886fad4b2
commit a0b211338c
4 changed files with 47 additions and 39 deletions
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10
tdc/rtl/clk_gen.v
View File

@@ -1,11 +1,17 @@
`default_nettype none
// dummy clock generator, should be replaced by a PLL clock gen eventually
module clk_gen(
module clk_gen #(parameter DIVISION=22)(
input wire i_clk,
output wire o_clk
);
assign o_clk = i_clk;
reg [DIVISION-1:0] counter = 0;
always @(posedge i_clk) begin
counter <= counter + 1;
end
assign o_clk = counter[DIVISION-1];
endmodule
// Local Variables:

41
tdc/rtl/top.v
View File

@@ -2,41 +2,42 @@
module top #(parameter WIDTH=24)(
input wire i_clk,
output wire o_led,
input wire i_start,
input wire i_stop,
input wire i_startN,
input wire i_stopN,
input wire i_resetN,
output wire o_ready,
output wire [15:0] o_data,
output wire o_ledN,
output wire o_readyN,
output wire [5:0] o_dataN,
output wire o_led_row_0
);
wire clk_12MHz;
wire clk_3Hz;
reg buf_led = 0;
wire buf_ready;
wire [5:0] buf_data;
assign o_readyN = ~buf_ready;
assign o_dataN = ~buf_data;
clk_gen clk_gen_0 (/*autoinst*/
clk_gen #(.DIVISION(22)) clk_gen0 (/*autoinst*/
// Outputs
.o_clk (clk_12MHz),
.o_clk (clk_3Hz),
// Inputs
.i_clk (i_clk));
tdc tdc0(/*autoinst*/
tdc #(.COUNTER_WIDTH(6)) tdc0 (/*autoinst*/
// Outputs
.o_ready (o_ready),
.o_data (o_data[15:0]),
.o_ready (buf_ready),
.o_data (buf_data),
// Inputs
.i_clk (clk_12MHz),
.i_start (i_start),
.i_stop (i_stop),
.i_clk (clk_3Hz),
.i_start (~i_startN),
.i_stop (~i_stopN),
.i_reset (~i_resetN));
reg [WIDTH-1:0] counter;
always @(posedge clk_12MHz) begin
counter <= counter + 1'b1;
buf_led <= counter[WIDTH-1];
always @(posedge clk_3Hz) begin
buf_led <= ~buf_led;
end
assign o_led = ~buf_led;
assign o_ledN = ~buf_led;
assign o_led_row_0 = 1'b0;
endmodule