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calib delay?

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Nam Tran
2020-12-16 15:01:39 -06:00
parent e7a23afcb0
commit 99a8661faa
2 changed files with 33 additions and 22 deletions
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44
tdc/rtl/top.v
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@@ -1,10 +1,12 @@
`default_nettype none `default_nettype none
/* verilator lint_off UNUSED */
module top #(parameter WIDTH=24)( module top #(parameter WIDTH=24)(
input wire i_clk, input wire i_clk,
input wire i_startN, input wire i_startN,
input wire i_stopN, input wire i_stopN,
input wire i_resetN, input wire i_resetN,
// input wire [31:0] i_calib_delay,
output wire o_ledN, output wire o_ledN,
output wire o_readyN, output wire o_readyN,
output wire [5:0] o_dataN, output wire [5:0] o_dataN,
@@ -27,10 +29,26 @@ module top #(parameter WIDTH=24)(
.i_clk (i_clk)); .i_clk (i_clk));
/* verilator lint_on PINMISSING */ /* verilator lint_on PINMISSING */
reg db_start, db_stop; reg db_start, db_stop;
always @(posedge clk_100MHz) begin reg [31:0] cal_delay = 15000;
db_start <= ~i_startN; wire aa;
db_stop <= ~i_stopN; debounce db1 (
end .db (aa),
.clk (clk_100MHz),
.reset (~i_resetN),
.sw (~i_startN ));
tdc_calib tcalib (
.o_calib_start (db_start),
.o_calib_stop (db_stop),
.i_clk (i_clk),
// .i_delay (i_calib_delay),
.i_delay (cal_delay),
.i_start_btn (aa),
.i_resetN (i_resetN)
);
// always @(posedge clk_100MHz) begin
// db_start <= ~i_startN;
// db_stop <= ~i_stopN;
// end
`ifdef DEBOUNCE `ifdef DEBOUNCE
debounce db1 ( debounce db1 (
// Outputs // Outputs
@@ -65,21 +83,21 @@ module top #(parameter WIDTH=24)(
assign o_ledN = ~buf_led; assign o_ledN = ~buf_led;
assign o_led_row_0 = 1'b0; assign o_led_row_0 = 1'b0;
parameter CLOCK_RATE_HZ = 100_000_000; // 100MHz clock parameter CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
parameter BAUD_RATE = 115_200; // 115.2 KBaud parameter BAUD_RATE = 115_200; // 115.2 KBaud
parameter INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE); parameter INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
// transferring data out every second // transferring data out every second
wire tx_start; wire tx_start;
pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start)); pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start));
wire tx_busy; wire tx_busy;
reg tx_stb; reg tx_stb;
reg [2:0] tx_index; reg [2:0] tx_index;
reg [7:0] tx_data; reg [7:0] tx_data;
// there are 4bytes to transmit // there are 4bytes to transmit
initial tx_index = 3'd0; initial tx_index = 3'd0;
always @(posedge clk_100MHz) begin always @(posedge clk_100MHz) begin
if ((tx_stb)&&(!tx_busy)) if ((tx_stb)&&(!tx_busy))
tx_index <= tx_index + 1'b1; tx_index <= tx_index + 1'b1;
@@ -96,7 +114,7 @@ module top #(parameter WIDTH=24)(
3'd7: tx_data <= "f"; 3'd7: tx_data <= "f";
endcase endcase
end end
initial tx_stb = 1'b0; initial tx_stb = 1'b0;
// transmit only when data is ready // transmit only when data is ready
always @(posedge clk_100MHz) begin always @(posedge clk_100MHz) begin
if (tx_start) if (tx_start)

11
tdc/sim/top.cc
View File

@@ -53,21 +53,14 @@ int main(int argc, char **argv) {
const unsigned int db_clk_Hz = 10; // 10 ms -> 10 Hz const unsigned int db_clk_Hz = 10; // 10 ms -> 10 Hz
const unsigned int db_ticks = main_clk_Hz / db_clk_Hz; const unsigned int db_ticks = main_clk_Hz / db_clk_Hz;
// tb->i_calib_delay = 20;
// start pulse // start pulse
tb->i_startN = 0; tb->i_startN = 0;
tick(++tickcount, tb, tfp); tick(++tickcount, tb, tfp);
tb->i_startN = 1; tb->i_startN = 1;
for (int k = 0; k < 394; k++) // for (int k = 0; k < tb->i_calib_delay + 10; k++)
tick(++tickcount, tb, tfp); tick(++tickcount, tb, tfp);
for (int k = 0; k < (1<<17); k++)
tick(++tickcount, tb, tfp);
// stop pulse
tb->i_stopN = 0;
tick(++tickcount, tb, tfp);
tb->i_stopN = 1;
for (int k = 0; k < (1<<16); k++) for (int k = 0; k < (1<<16); k++)
tick(++tickcount, tb, tfp); tick(++tickcount, tb, tfp);