diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v
index 61aaa70..22a88a4 100644
--- a/tdc/rtl/top.v
+++ b/tdc/rtl/top.v
@@ -1,10 +1,12 @@
 `default_nettype  none
 
+/* verilator lint_off UNUSED */
 module top #(parameter WIDTH=24)(
    input wire i_clk,
    input wire i_startN,
    input wire i_stopN,
    input wire i_resetN,
+   // input wire [31:0] i_calib_delay,
    output wire o_ledN,
    output wire o_readyN,
    output wire [5:0] o_dataN,
@@ -27,10 +29,26 @@ module top #(parameter WIDTH=24)(
    .i_clk            (i_clk));
    /* verilator lint_on PINMISSING */
    reg db_start, db_stop;
-   always @(posedge clk_100MHz) begin
-      db_start <= ~i_startN;
-      db_stop <= ~i_stopN;
-   end
+   reg [31:0] cal_delay = 15000;
+   wire aa;
+   debounce db1 (
+      .db                       (aa),
+      .clk                      (clk_100MHz),
+      .reset                    (~i_resetN),
+      .sw                       (~i_startN ));
+   tdc_calib tcalib (
+      .o_calib_start     (db_start),
+      .o_calib_stop      (db_stop),
+      .i_clk             (i_clk),
+      // .i_delay           (i_calib_delay),
+      .i_delay           (cal_delay),
+      .i_start_btn       (aa),
+      .i_resetN          (i_resetN)
+   );
+   // always @(posedge clk_100MHz) begin
+      // db_start <= ~i_startN;
+      // db_stop <= ~i_stopN;
+   // end
 `ifdef DEBOUNCE
    debounce db1 (
       // Outputs
@@ -65,21 +83,21 @@ module top #(parameter WIDTH=24)(
    assign o_ledN = ~buf_led;
    assign o_led_row_0 = 1'b0;
 
-   parameter	CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
-   parameter	BAUD_RATE = 115_200; // 115.2 KBaud
-   parameter	INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
+   parameter    CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
+   parameter    BAUD_RATE = 115_200; // 115.2 KBaud
+   parameter    INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
 
    // transferring data out every second
    wire tx_start;
    pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start));
 
-   wire		tx_busy;
-   reg		tx_stb;
-   reg	[2:0]	tx_index;
-   reg	[7:0]	tx_data;
+   wire         tx_busy;
+   reg          tx_stb;
+   reg  [2:0]   tx_index;
+   reg  [7:0]   tx_data;
 
    // there are 4bytes to transmit
-   initial	tx_index = 3'd0;
+   initial      tx_index = 3'd0;
    always @(posedge clk_100MHz) begin
       if ((tx_stb)&&(!tx_busy))
          tx_index <= tx_index + 1'b1;
@@ -96,7 +114,7 @@ module top #(parameter WIDTH=24)(
          3'd7: tx_data <= "f";
       endcase
    end
-   initial	tx_stb = 1'b0;
+   initial      tx_stb = 1'b0;
    // transmit only when data is ready
    always @(posedge clk_100MHz) begin
       if (tx_start)
diff --git a/tdc/sim/top.cc b/tdc/sim/top.cc
index 7746a8c..1bee09f 100644
--- a/tdc/sim/top.cc
+++ b/tdc/sim/top.cc
@@ -53,21 +53,14 @@ int main(int argc, char **argv) {
    const unsigned int db_clk_Hz = 10; // 10 ms -> 10 Hz
    const unsigned int db_ticks = main_clk_Hz / db_clk_Hz;
 
+   // tb->i_calib_delay = 20;
    // start pulse
-
    tb->i_startN = 0;
    tick(++tickcount, tb, tfp);
    tb->i_startN = 1;
 
-   for (int k = 0; k < 394; k++) 
+   // for (int k = 0; k < tb->i_calib_delay + 10; k++) 
       tick(++tickcount, tb, tfp);
-   for (int k = 0; k < (1<<17); k++) 
-      tick(++tickcount, tb, tfp);
-
-   // stop pulse
-   tb->i_stopN = 0;
-   tick(++tickcount, tb, tfp);
-   tb->i_stopN = 1;
 
    for (int k = 0; k < (1<<16); k++) 
       tick(++tickcount, tb, tfp);