assign reg in always block

2020-10-23 15:18:09 -05:00
parent 70d8ea268e
commit 66010c90d9
1 changed files with 2 additions and 2 deletions
--- a/fsm/rtl/top.v
+++ b/fsm/rtl/top.v
@@ -32,8 +32,8 @@ module top(i_clk, o_led, lcol1);
         obuf <= {obuf[6:0], obuf[7]}; // left shift
         // obuf <= {obuf[0], obuf[7:1]}; // right shift
-   always @(*)
+   always @(posedge clk_12MHz)
-      o_led = ~obuf;
+      o_led <= ~obuf;
   assign lcol1 = 1'b0;
 endmodule