hack to use PLL in synthesizing, and fake 100 MHz on verilator

tdc/rtl/pll_100MHz.v

@@ -0,0 +1,40 @@
+/**
+* PLL configuration
+*
+* This Verilog module was generated automatically
+* using the icepll tool from the IceStorm project.
+* Use at your own risk.
+*
+* Given input frequency:        12.000 MHz
+* Requested output frequency:  100.000 MHz
+* Achieved output frequency:   100.500 MHz
+*/
+// this module is skipped by verilator
+`ifdef VERILATOR
+`else
+   module pll_100MHz(
+      input  i_clk,
+      output o_clk_100MHz,
+      output o_pll_locked
+   );
+
+   wire clk_int;
+   SB_PLL40_CORE #(
+      .FEEDBACK_PATH("SIMPLE"),
+      .DIVR(4'b0000),		// DIVR =  0
+      .DIVF(7'b1000010),	// DIVF = 66
+      .DIVQ(3'b011),		// DIVQ =  3
+      .FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+   ) uut (
+      .LOCK(o_pll_locked),
+      .RESETB(1'b1),
+      .BYPASS(1'b0),
+      .REFERENCECLK(i_clk),
+      .PLLOUTCORE(clk_int)
+   );
+
+   SB_GB sbGlobalBuffer_inst( .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_int),
+      .GLOBAL_BUFFER_OUTPUT(o_clk_100MHz));
+
+endmodule
+`endif