hack to use PLL in synthesizing, and fake 100 MHz on verilator

tdc/rtl/clk_gen.v

@@ -2,17 +2,29 @@
 // dummy clock generator, should be replaced by a PLL clock gen eventually
 module clk_gen #(parameter DIVISION=22)(
    input wire i_clk,
-   output wire o_clk
+   output wire o_clk_100MHz,
+   output wire o_div_clk
 );
 
-reg [DIVISION-1:0] counter = 0;
+/* verilator lint_off PINCONNECTEMPTY */
+/* verilator lint_off PINMISSING */
+   reg [DIVISION-1:0] counter = 0;
+`ifdef VERILATOR
+   always @(posedge i_clk) begin
+      counter <= counter + 1;
+   end
 
-always @(posedge i_clk) begin
-   counter <= counter + 1;
-end
-
-assign o_clk = counter[DIVISION-1];
+   assign o_clk_100MHz = i_clk;
+`else
+   pll_100MHz pll0(.i_clk(i_clk), .o_clk_100MHz(o_clk_100MHz), .o_pll_locked());
+   always @(posedge o_clk_100MHz) begin
+      counter <= counter + 1;
+   end
+`endif
 
+   assign o_div_clk = counter[DIVISION-1];
+/* verilator lint_on PINCONNECTEMPTY */
+/* verilator lint_on PINMISSING */
 endmodule
 // Local Variables:
 // verilog-library-directories:(".." "./rtl" ".")