move debouncing parts to top module
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@@ -28,14 +28,30 @@ module top #(parameter WIDTH=24)(
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.i_clk (i_clk));
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/* verilator lint_on PINMISSING */
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reg db_start, db_stop;
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debounce db1 (
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// Outputs
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.db (db_start),
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// Inputs
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.clk (clk_100MHz),
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.reset (~i_resetN),
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.sw (~i_startN));
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debounce db2 (
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// Outputs
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.db (db_stop),
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// Inputs
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.clk (clk_100MHz),
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.reset (~i_resetN),
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.sw (~i_stopN));
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tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
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// Outputs
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.o_ready (buf_ready),
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.o_data (buf_data),
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// Inputs
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.i_clk (clk_100MHz),
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.i_start (~i_startN),
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.i_stop (~i_stopN),
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.i_start (db_start),
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.i_stop (db_stop),
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.i_reset (~i_resetN));
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always @(posedge clk_1Hz) begin
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