From 5a58da34afe8dfca289ef8639d68f774debedb72 Mon Sep 17 00:00:00 2001
From: Nam Tran <thnam.me@gmail.com>
Date: Tue, 27 Oct 2020 07:50:25 -0500
Subject: [PATCH] move debouncing parts to top module

---
 tdc/rtl/tdc.v | 21 +++------------------
 tdc/rtl/top.v | 20 ++++++++++++++++++--
 2 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/tdc/rtl/tdc.v b/tdc/rtl/tdc.v
index d62dca2..a0d70c9 100644
--- a/tdc/rtl/tdc.v
+++ b/tdc/rtl/tdc.v
@@ -12,21 +12,6 @@ module tdc #(parameter COUNTER_WIDTH=16)(
 reg [COUNTER_WIDTH-1:0] counter;
 assign o_data = counter;
 
-reg db_start, db_stop;
-debounce db1 (
-   // Outputs
-   .db                       (db_start),
-   // Inputs
-   .clk                      (i_clk),
-   .reset                    (i_reset),
-   .sw                       (i_start));
-debounce db2 (
-   // Outputs
-   .db                       (db_stop),
-   // Inputs
-   .clk                      (i_clk),
-   .reset                    (i_reset),
-   .sw                       (i_stop));
 // states
 localparam state_idle = 2'b00;
 localparam state_started = 2'b01;
@@ -48,19 +33,19 @@ end
 always @(*) begin
    case (current_state)
       state_idle: begin
-         if (db_start && (~db_stop))
+         if (i_start && (~i_stop))
             next_state <= state_started;
          else
             next_state <= state_idle;
       end
       state_started: begin
-         if (~db_start && (~db_stop))
+         if (~i_start && (~i_stop))
             next_state <= state_running;
          else
             next_state <= state_started;
       end
       state_running: begin
-         if (~db_start && (db_stop))
+         if (~i_start && (i_stop))
             next_state <= state_stopped;
          else
             next_state <= state_running;
diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v
index 17aedb3..edcb76f 100644
--- a/tdc/rtl/top.v
+++ b/tdc/rtl/top.v
@@ -28,14 +28,30 @@ module top #(parameter WIDTH=24)(
                       .i_clk            (i_clk));
 /* verilator lint_on PINMISSING */
 
+reg db_start, db_stop;
+debounce db1 (
+   // Outputs
+   .db                       (db_start),
+   // Inputs
+   .clk                      (clk_100MHz),
+   .reset                    (~i_resetN),
+   .sw                       (~i_startN));
+debounce db2 (
+   // Outputs
+   .db                       (db_stop),
+   // Inputs
+   .clk                      (clk_100MHz),
+   .reset                    (~i_resetN),
+   .sw                       (~i_stopN));
+
    tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
             // Outputs
             .o_ready                    (buf_ready),
             .o_data                     (buf_data),
             // Inputs
             .i_clk                      (clk_100MHz),
-            .i_start                    (~i_startN),
-            .i_stop                     (~i_stopN),
+            .i_start                    (db_start),
+            .i_stop                     (db_stop),
             .i_reset                   (~i_resetN));
 
    always @(posedge clk_1Hz) begin