tdc state machine

tdc/rtl/top.v

@@ -1,25 +1,42 @@
 `default_nettype  none
 
-module top(i_clk, o_led, o_led_row_0);
-   parameter WIDTH = 24;
-   input wire i_clk;
-   output wire o_led;
-   output wire o_led_row_0;
-
+module top #(parameter WIDTH=24)(
+   input wire i_clk,
+   output wire o_led,
+   input wire i_start,
+   input wire i_stop,
+   input wire i_resetN,
+   output wire o_ready,
+   output wire [15:0] o_data,
+   output wire o_led_row_0
+);
    wire clk_12MHz;
+   reg buf_led = 0;
 
    clk_gen clk_gen_0 (/*autoinst*/
-      // Outputs
-      .o_clk                 (clk_12MHz),
-      // Inputs
-      .i_clk                 (i_clk));
+                      // Outputs
+                      .o_clk            (clk_12MHz),
+                      // Inputs
+                      .i_clk            (i_clk));
+
+   tdc tdc0(/*autoinst*/
+            // Outputs
+            .o_ready                    (o_ready),
+            .o_data                     (o_data[15:0]),
+            // Inputs
+            .i_clk                      (clk_12MHz),
+            .i_start                    (i_start),
+            .i_stop                     (i_stop),
+            .i_reset                   (~i_resetN));
 
    reg [WIDTH-1:0] counter;
 
-   always @(posedge clk_12MHz)
+   always @(posedge clk_12MHz) begin
       counter <= counter + 1'b1;
+      buf_led <= counter[WIDTH-1];
+   end
 
-   assign o_led = counter[WIDTH-1];
+   assign o_led = ~buf_led;
    assign o_led_row_0 = 1'b0;
 endmodule