can transmit data out, but in wrong order ...

tdc/constraints/iceFUN.pcf

@@ -15,3 +15,4 @@ set_io --warn-no-port o_dataN[5] 	C7
 
 set_io --warn-no-port o_ledN 	A4
 set_io --warn-no-port o_readyN 	C4
+set_io --warn-no-port o_uart_tx A3

tdc/rtl/pos_edge_detector.v

@@ -0,0 +1,17 @@
+`default_nettype none
+module pos_edge_detector ( 
+   input wire i_sig,            // Input signal for which positive edge has to be detected
+   input wire i_clk,            // Input signal for clock
+   output wire o_pe);           // Output signal that gives a pulse when a positive edge occurs
+
+reg   sig_dly; // Internal signal to store the delayed version of signal
+
+// This always block ensures that sig_dly is exactly 1 clock behind sig
+always @ (posedge i_clk) begin
+   sig_dly <= i_sig;
+end
+
+// Combinational logic where sig is AND with delayed, inverted version of sig
+// Assign statement assigns the evaluated expression in the RHS to the internal net pe
+assign o_pe = i_sig & ~sig_dly;            
+endmodule 

tdc/rtl/top.v

@@ -8,18 +8,17 @@ module top #(parameter WIDTH=24)(
    output wire o_ledN,
    output wire o_readyN,
    output wire [5:0] o_dataN,
-   output wire o_led_row_0
+   output wire o_led_row_0,
+   output wire o_uart_tx
 );
    wire clk_1Hz; // 1.4 Hz actually
    wire clk_100MHz;
    reg buf_led = 0;
    wire buf_ready;
-   /* verilator lint_off UNUSED */
+   parameter TDC_COUNTER_WIDTH = 32;
-   parameter TDC_COUNTER_WIDTH = 28;
    wire [TDC_COUNTER_WIDTH-1:0] buf_data;
    assign o_readyN = ~buf_ready;
    assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
-   /* verilator lint_on UNUSED */
 
    /* verilator lint_off PINMISSING */
    clk_gen #(.DIVISION(26)) clk_gen0 (
@@ -28,6 +27,7 @@ module top #(parameter WIDTH=24)(
    .i_clk            (i_clk));
    /* verilator lint_on PINMISSING */
    reg db_start, db_stop;
+   // skipping the debouncing in simulation
 `ifdef VERILATOR
    always @(posedge clk_100MHz) begin
       db_start <= ~i_startN;
@@ -66,6 +66,50 @@ module top #(parameter WIDTH=24)(
 
    assign o_ledN = ~buf_led;
    assign o_led_row_0 = 1'b0;
+
+   parameter	CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
+   parameter	BAUD_RATE = 115_200; // 115.2 KBaud
+   parameter	INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
+
+   // transferring data out every second
+   wire tx_start;
+   pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start));
+
+   wire		tx_busy;
+   reg		tx_stb;
+   reg	[2:0]	tx_index;
+   reg	[7:0]	tx_data;
+
+   // there are 4bytes to transmit
+   initial	tx_index = 3'h0;
+   always @(posedge clk_100MHz) begin
+      if ((tx_stb)&&(!tx_busy)) begin
+         if (tx_index < 3'd4)
+            tx_index <= tx_index + 1'b1;
+         else
+            tx_index <= 0;
+      end
+   end
+   always @(posedge clk_100MHz) begin
+      case(tx_index)
+         3'd1: tx_data <= buf_data[31:24];
+         3'd2: tx_data <= buf_data[23:16];
+         3'd3: tx_data <= buf_data[15:8];
+         3'd4: tx_data <= buf_data[7:0];
+      endcase
+   end
+   initial	tx_stb = 1'b0;
+   // transmit only when data is ready
+   always @(posedge clk_100MHz) begin
+      if (tx_start)
+         tx_stb <= 1'b1;
+      else if ((tx_stb)&&(!tx_busy)&&(tx_index==3'd4))
+         tx_stb <= 1'b0;
+   end
+
+   txuart #(INITIAL_UART_SETUP[23:0]) transmitter(clk_100MHz,
+      tx_stb, tx_data, o_uart_tx, tx_busy);
+
 endmodule
 
 // Local Variables:

tdc/rtl/txuart.v

@@ -0,0 +1,141 @@
+`default_nettype	none
+module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy);
+	parameter	[23:0]	CLOCKS_PER_BAUD = 24'd868;
+	input	wire		i_clk;
+	input	wire		i_wr;
+	input	wire	[7:0]	i_data;
+	// And the UART output line itself
+	output	wire		o_uart_tx;
+	// A line to tell others when we are ready to accept data.  If
+	// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
+	// for transmission.
+	output	reg		o_busy;
+
+	// Define several states
+	localparam [3:0] START	= 4'h0,
+		BIT_ZERO	= 4'h1,
+		BIT_ONE		= 4'h2,
+		BIT_TWO		= 4'h3,
+		BIT_THREE	= 4'h4,
+		BIT_FOUR	= 4'h5,
+		BIT_FIVE	= 4'h6,
+		BIT_SIX		= 4'h7,
+		BIT_SEVEN	= 4'h8,
+		LAST		= 4'h8,
+		IDLE		= 4'hf;
+
+	reg	[23:0]	counter;
+	reg	[3:0]	state;
+	reg	[8:0]	lcl_data;
+	reg		baud_stb;
+
+	// o_busy
+	//
+	// This is a register, designed to be true is we are ever busy above.
+	// originally, this was going to be true if we were ever not in the
+	// idle state.  The logic has since become more complex, hence we have
+	// a register dedicated to this and just copy out that registers value.
+
+	initial	o_busy = 1'b0;
+	initial	state  = IDLE;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		// Immediately start us off with a start bit
+		{ o_busy, state } <= { 1'b1, START };
+	else if (baud_stb)
+	begin
+		if (state == IDLE) // Stay in IDLE
+			{ o_busy, state } <= { 1'b0, IDLE };
+		else if (state < LAST) begin
+			o_busy <= 1'b1;
+			state <= state + 1'b1;
+		end else // Wait for IDLE
+			{ o_busy, state } <= { 1'b1, IDLE };
+	end
+
+
+
+	// lcl_data
+	//
+	// This is our working copy of the i_data register which we use
+	// when transmitting.  It is only of interest during transmit, and is
+	// allowed to be whatever at any other time.  Hence, if o_busy isn't
+	// true, we can always set it.  On the one clock where o_busy isn't
+	// true and i_wr is, we set it and o_busy is true thereafter.
+	// Then, on any baud_stb (i.e. change between baud intervals)
+	// we simple logically shift the register right to grab the next bit.
+	initial	lcl_data = 9'h1ff;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+		lcl_data <= { i_data, 1'b0 };
+	else if (baud_stb)
+		lcl_data <= { 1'b1, lcl_data[8:1] };
+
+	// o_uart_tx
+	//
+	// This is the final result/output desired of this core.  It's all
+	// centered about o_uart_tx.  This is what finally needs to follow
+	// the UART protocol.
+	//
+	assign	o_uart_tx = lcl_data[0];
+
+
+	// All of the above logic is driven by the baud counter.  Bits must last
+	// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
+	// make certain of that.
+	//
+	// The basic logic is this: at the beginning of a bit interval, start
+	// the baud counter and set it to count CLOCKS_PER_BAUD.  When it gets
+	// to zero, restart it.
+	//
+	// However, comparing a 28'bit number to zero can be rather complex--
+	// especially if we wish to do anything else on that same clock.  For
+	// that reason, we create "baud_stb".  baud_stb is
+	// nothing more than a flag that is true anytime baud_counter is zero.
+	// It's true when the logic (above) needs to step to the next bit.
+	// Simple enough?
+	//
+	// I wish we could stop there, but there are some other (ugly)
+	// conditions to deal with that offer exceptions to this basic logic.
+	//
+	// 1. When the user has commanded a BREAK across the line, we need to
+	// wait several baud intervals following the break before we start
+	// transmitting, to give any receiver a chance to recognize that we are
+	// out of the break condition, and to know that the next bit will be
+	// a stop bit.
+	//
+	// 2. A reset is similar to a break condition--on both we wait several
+	// baud intervals before allowing a start bit.
+	//
+	// 3. In the idle state, we stop our counter--so that upon a request
+	// to transmit when idle we can start transmitting immediately, rather
+	// than waiting for the end of the next (fictitious and arbitrary) baud
+	// interval.
+	//
+	// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
+	// the idle state, but we also just accepted a command to start writing
+	// the next word.  At this point, the baud counter needs to be reset
+	// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
+	//
+	// The logic is a bit twisted here, in that it will only check for the
+	// above condition when baud_stb is false--so as to make
+	// certain the STOP bit is complete.
+	initial	baud_stb = 1'b1;
+	initial	counter = 0;
+	always @(posedge i_clk)
+	if ((i_wr)&&(!o_busy))
+	begin
+		counter  <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end else if (!baud_stb)
+	begin
+		baud_stb <= (counter == 24'h01);
+		counter  <= counter - 1'b1;
+	end else if (state != IDLE)
+	begin
+		counter <= CLOCKS_PER_BAUD - 1'b1;
+		baud_stb <= 1'b0;
+	end
+
+endmodule
+

tdc/sim/top.cc

@@ -67,13 +67,13 @@ int main(int argc, char **argv) {
    tick(++tickcount, tb, tfp);
    tb->i_stopN = 1;
 
-   for (int k = 0; k < 30; k++) 
+   for (int k = 0; k < (1<<16); k++) 
       tick(++tickcount, tb, tfp);
 
    tb->i_resetN = 0;
    tick(++tickcount, tb, tfp);
    tb->i_resetN = 1;
 
-   for (int k = 0; k < 3; k++) 
+   for (int k = 0; k < 30; k++) 
       tick(++tickcount, tb, tfp);
 }