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shift right as well

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Nam Tran
2020-10-23 14:50:34 -05:00
parent 45160b50a9
commit 400ebbb9aa
1 changed files with 3 additions and 2 deletions
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5
fsm/rtl/top.v
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@@ -26,10 +26,11 @@ module top(i_clk, o_led, lcol1);
always @(posedge clk_12MHz) always @(posedge clk_12MHz)
{strobe, counter} <= counter + 1'b1; {strobe, counter} <= counter + 1'b1;
// shifting bit, to the left // shifting bit
always @(posedge clk_12MHz) always @(posedge clk_12MHz)
if (strobe) if (strobe)
obuf <= {obuf[6:0], obuf[7]}; obuf <= {obuf[6:0], obuf[7]}; // left shift
// obuf <= {obuf[0], obuf[7:1]}; // right shift
always @(*) always @(*)
o_led = ~obuf; o_led = ~obuf;