another uart demonstration: uart echo module

uart/bench/uart_tx_tb.v

@@ -0,0 +1,63 @@
+`timescale 1ns/1ps
+`define IVERILOG 1
+
+module uart_tx_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire                    tx_done_o;              // From uut of uart_tx.v
+wire                    tx_o;                   // From uut of uart_tx.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_tx.v
+reg [7:0]               data_i;                 // To uut of uart_tx.v
+reg                     en_i;                   // To uut of uart_tx.v
+reg                     rst_n;                  // To uut of uart_tx.v
+// End of automatics
+localparam CLK_PERIOD = 10;
+uart_tx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD              (CLK_PERIOD - 1)) uut (/*autoinst*/
+            // Outputs
+            .tx_o           (tx_o),
+            .tx_done_o      (tx_done_o),
+            // Inputs
+            .clk            (clk),
+            .rst_n          (rst_n),
+            .en_i           (en_i),
+            .data_i         (data_i[7:0]));
+
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+    data_i = 0;
+end
+
+always
+    #(CLK_PERIOD/2) clk = ~clk;
+
+initial begin
+    #(CLK_PERIOD);
+
+    rst_n = 0;
+    #(CLK_PERIOD);
+    rst_n = 1;
+    #(CLK_PERIOD);
+
+    data_i = 8'h55;
+    en_i = 1;
+    #(CLK_PERIOD);
+
+    en_i = 0;
+    #(200 * CLK_PERIOD);
+
+    #400 $finish; // finish at 200 ticks
+end
+endmodule // end of uart_tx_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End: