another uart demonstration: uart echo module

uart/bench/uart_rx_tb.v

@@ -0,0 +1,78 @@
+`timescale 1ns/1ps
+`define IVERILOG 1
+`default_nettype none
+
+module uart_rx_tb;
+/*autowire*/
+// Beginning of automatic wires (for undeclared instantiated-module outputs)
+wire [7:0]              data_o;                 // From uut of uart_rx.v
+wire                    rx_done_o;              // From uut of uart_rx.v
+// End of automatics
+/*autoreginput*/
+// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+reg                     clk;                    // To uut of uart_rx.v
+reg                     rst_n;                  // To uut of uart_rx.v
+reg                     rx_i;                   // To uut of uart_rx.v
+// End of automatics
+
+localparam clk_period = 20;
+localparam clocks_per_baud = 20;
+uart_rx #(/*autoinstparam*/
+            // Parameters
+            .CLOCKS_PER_BAUD              (clocks_per_baud - 1))
+        uut (/*autoinst*/
+            // Outputs
+            .data_o         (data_o[7:0]),
+            .rx_done_o      (rx_done_o),
+            // Inputs
+            .clk            (clk),
+            .rst_n          (rst_n),
+            .rx_i           (rx_i));
+
+initial begin
+    $dumpfile("build/waveform.vcd");
+    $dumpvars(0, uut);
+
+    clk = 1'b1;
+    rst_n = 1'b1;
+    rx_i = 1'b1;
+end
+
+always
+    #(clk_period/2) clk = ~clk;
+
+initial begin
+    #clk_period;
+    rst_n = 0; // start reset
+    #clk_period;
+    rst_n = 1; // finish reset
+    #(clk_period * 50);
+
+    rx_i = 0; // start bit
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 0
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 1
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 2
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 3
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 4
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 5
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // bit 6
+    #(clk_period * clocks_per_baud);
+    rx_i = 0; // bit 7
+    #(clk_period * clocks_per_baud);
+    rx_i = 1; // stop bit
+    #(clk_period * clocks_per_baud);
+
+    #800 $finish; // finish at 200 ticks
+end
+endmodule // end of uart_rx_tb
+
+          // Local Variables:
+          // verilog-library-directories:(".." "../rtl" ".")
+          // End: