minimal change from https://zipcpu.com/tutorial/ex-04-reqwalker.tgz
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118
wb-tut4/sim/top.cc
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118
wb-tut4/sim/top.cc
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#include <stdio.h>
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#include <stdlib.h>
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#include "Vtop.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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int tickcount = 0;
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Vtop *tb;
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VerilatedVcdC *tfp;
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void tick(void) {
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tickcount++;
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10 - 2);
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tb->i_clk = 1;
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tb->eval();
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if (tfp)
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tfp->dump(tickcount * 10);
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tb->i_clk = 0;
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tb->eval();
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if (tfp) {
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tfp->dump(tickcount * 10 + 5);
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tfp->flush();
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}
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}
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unsigned wb_read(unsigned a) {
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tb->i_cyc = tb->i_stb = 1;
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tb->i_we = 0;
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tb->eval();
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tb->i_addr= a;
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// Make the request
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while(tb->o_stall)
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tick();
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tick();
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tb->i_stb = 0;
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// Wait for the ACK
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while(!tb->o_ack)
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tick();
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// Idle the bus, and read the response
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tb->i_cyc = 0;
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return tb->o_data;
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}
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void wb_write(unsigned a, unsigned v) {
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tb->i_cyc = tb->i_stb = 1;
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tb->i_we = 1;
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tb->eval();
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tb->i_addr= a;
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tb->i_data= v;
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// if busy, keep ticking
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while(tb->o_stall)
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tick();
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// Then, make the bus request
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tick();
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// and pull stb down
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tb->i_stb = 0;
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// Wait for the acknowledgement
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while(!tb->o_ack)
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tick();
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// Idle the bus and return
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tb->i_cyc = tb->i_stb = 0;
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}
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int main(int argc, char **argv) {
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int last_led, last_state = 0, state = 0;
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// Call commandArgs first!
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Verilated::commandArgs(argc, argv);
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// Instantiate our design
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tb = new Vtop;
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// Generate a trace
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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tb->trace(tfp, 99);
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tfp->open("build/waveform.vcd");
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last_led = tb->o_led;
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// Read from the current state
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printf("Initial state is: 0x%02x\n",
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wb_read(0));
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for(int cycle=0; cycle<2; cycle++) {
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// Wait five clocks
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for(int i=0; i<5; i++)
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tick();
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// Start the LEDs cycling
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wb_write(0,0);
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tick();
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while((state = wb_read(0))!=0) {
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if ((state != last_state)
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||(tb->o_led != last_led)) {
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printf("%6d: State #%2d ",
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tickcount, state);
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for(int j=0; j<6; j++) {
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if(tb->o_led & (1<<j))
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printf("O");
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else
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printf("-");
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} printf("\n");
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} tick();
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last_state = state;
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last_led = tb->o_led;
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}
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}
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tfp->close();
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delete tfp;
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delete tb;
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}
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13
wb-tut4/sim/top.sby
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13
wb-tut4/sim/top.sby
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@@ -0,0 +1,13 @@
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[options]
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mode prove
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[engines]
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smtbmc
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[script]
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read -formal *.v
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prep -top top
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[files]
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rtl/top.v
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rtl/clk_gen.v
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