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add clock constraint, amend Makefile

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Nam Tran
2020-10-23 11:49:21 -05:00
parent 42c5b8a47f
commit 12829a3e9c
2 changed files with 5 additions and 3 deletions
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7
blinky/Makefile
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@@ -16,7 +16,7 @@ all: $(SIM_TARGET) $(BIN_TARGET)
# -GWIDTH=5 allows passing parameter to verilog module
obj_dir/Vblinky.cpp: blinky.v
@echo "Running verilator"
@$(VERILATOR) --trace -Wall -GWIDTH=15 -cc blinky.v
@$(VERILATOR) --trace -Wall -GWIDTH=15 -cc blinky.v --timescale-override 10ns/1ns
obj_dir/Vblinky__ALL.a: obj_dir/Vblinky.cpp
@make --no-print-directory -C obj_dir -f Vblinky.mk
@@ -27,13 +27,14 @@ $(SIM_TARGET): blinky.cpp obj_dir/Vblinky__ALL.a
@mkdir -p build
@g++ -I$(VINC) -I obj_dir -std=c++11 $(VINC)/verilated.cpp $(VINC)/verilated_vcd_c.cpp \
$^ -o $@
@echo "Run simulation with ./$(TARGET)"
@echo "Run simulation with ./$(SIM_TARGET)"
$(BIN_TARGET): blinky.v $(PCF)
@echo "Building binary stream"
@$(YOSYS) -p "synth_ice40 -top blinky -json build/blinky.json" -q $<
@$(PNR) -r --hx8k --json build/blinky.json --package cb132 \
--asc build/blinky.asc --opt-timing --pcf $(PCF) -q
--asc build/blinky.asc --opt-timing --pcf $(PCF)\
--pre-pack clock_constraints.py -l build/pnr_report.txt -q
@$(IPACK) build/blinky.asc build/blinky.bin
burn: $(BIN_TARGET)

1
blinky/clock_constraints.py Normal file
View File

@@ -0,0 +1 @@
ctx.addClock("i_clk", 100)