From 12829a3e9c4d602cc7275fc1fc20c050d9cf4a24 Mon Sep 17 00:00:00 2001 From: Nam Tran Date: Fri, 23 Oct 2020 11:49:21 -0500 Subject: [PATCH] add clock constraint, amend Makefile --- blinky/Makefile | 7 ++++--- blinky/clock_constraints.py | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) create mode 100644 blinky/clock_constraints.py diff --git a/blinky/Makefile b/blinky/Makefile index 28bed39..5509cb4 100644 --- a/blinky/Makefile +++ b/blinky/Makefile @@ -16,7 +16,7 @@ all: $(SIM_TARGET) $(BIN_TARGET) # -GWIDTH=5 allows passing parameter to verilog module obj_dir/Vblinky.cpp: blinky.v @echo "Running verilator" - @$(VERILATOR) --trace -Wall -GWIDTH=15 -cc blinky.v + @$(VERILATOR) --trace -Wall -GWIDTH=15 -cc blinky.v --timescale-override 10ns/1ns obj_dir/Vblinky__ALL.a: obj_dir/Vblinky.cpp @make --no-print-directory -C obj_dir -f Vblinky.mk @@ -27,13 +27,14 @@ $(SIM_TARGET): blinky.cpp obj_dir/Vblinky__ALL.a @mkdir -p build @g++ -I$(VINC) -I obj_dir -std=c++11 $(VINC)/verilated.cpp $(VINC)/verilated_vcd_c.cpp \ $^ -o $@ - @echo "Run simulation with ./$(TARGET)" + @echo "Run simulation with ./$(SIM_TARGET)" $(BIN_TARGET): blinky.v $(PCF) @echo "Building binary stream" @$(YOSYS) -p "synth_ice40 -top blinky -json build/blinky.json" -q $< @$(PNR) -r --hx8k --json build/blinky.json --package cb132 \ - --asc build/blinky.asc --opt-timing --pcf $(PCF) -q + --asc build/blinky.asc --opt-timing --pcf $(PCF)\ + --pre-pack clock_constraints.py -l build/pnr_report.txt -q @$(IPACK) build/blinky.asc build/blinky.bin burn: $(BIN_TARGET) diff --git a/blinky/clock_constraints.py b/blinky/clock_constraints.py new file mode 100644 index 0000000..f949a2c --- /dev/null +++ b/blinky/clock_constraints.py @@ -0,0 +1 @@ +ctx.addClock("i_clk", 100)