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make sure the verification works

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Nam Tran
2020-10-23 19:27:49 -05:00
parent 5f18f8f88c
commit 0a724d30d0
1 changed files with 1 additions and 0 deletions
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fsm/rtl/top.v
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@@ -22,6 +22,7 @@ module top(i_clk, o_led, lcol1);
initial begin initial begin
obuf = 8'h1; obuf = 8'h1;
{strobe, counter} = 0; {strobe, counter} = 0;
led_index = 0;
end end
always @(posedge clk_12MHz) always @(posedge clk_12MHz)