128 lines
3.4 KiB
Verilog
128 lines
3.4 KiB
Verilog
`default_nettype none
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module top(i_clk, o_led, o_led_row_0, i_request, o_busy);
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parameter WIDTH = 22;
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input wire i_clk;
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output wire [5:0] o_led;
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output wire o_led_row_0;
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input wire i_request;
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output wire o_busy;
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wire clk_12MHz;
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clk_gen clk_gen_0 (/*autoinst*/
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// Outputs
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.o_clk (clk_12MHz),
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// Inputs
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.i_clk (i_clk));
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reg [WIDTH-1:0] counter;
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reg [3:0] state;
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reg [5:0] led_buf; // output buffer, take into account the icefun use active low LED
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// reg strobe;
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reg busy_buf;
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wire req_buf;
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assign o_busy = ~busy_buf;
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assign o_led = ~led_buf;
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assign o_led_row_0 = 1'b0;
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assign req_buf = ~i_request;
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initial begin
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led_buf = 6'h0;
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// {strobe, counter} = 0;
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counter = 0;
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state = 0;
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busy_buf = 0;
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end
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always @(posedge clk_12MHz) begin
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if (!busy_buf && req_buf)
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busy_buf <= 1;
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else
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busy_buf <= (state != 4'h0);
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end
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// counter and strobe run only during busy signal is High
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always @(posedge clk_12MHz) begin
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if (busy_buf)
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counter <= counter + 1'b1;
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// {strobe, counter} <= counter + 1'b1;
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else
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// {strobe, counter} <= 0;
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counter <= 0;
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end
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// state change once strobe starts
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always @(posedge clk_12MHz) begin
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if (!busy_buf && req_buf)
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state <= 4'h1;
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else if (state >= 4'hB)
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state <= 4'h0;
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else if (state != 0)
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state <= state + 1'b1;
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end
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// fsm for led_buf
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always @(posedge clk_12MHz) begin
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// if (strobe)
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case (state)
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4'h1: led_buf <= 6'b00_0001;
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4'h2: led_buf <= 6'b00_0010;
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4'h3: led_buf <= 6'b00_0100;
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4'h4: led_buf <= 6'b00_1000;
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4'h5: led_buf <= 6'b01_0000;
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4'h6: led_buf <= 6'b10_0000;
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4'h7: led_buf <= 6'b01_0000;
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4'h8: led_buf <= 6'b00_1000;
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4'h9: led_buf <= 6'b00_0100;
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4'ha: led_buf <= 6'b00_0010;
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4'hb: led_buf <= 6'b00_0001;
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default: led_buf <= 6'b00_0000;
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endcase
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end
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`ifdef FORMAL
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// state should never go beyond 13
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always @(*)
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assert(state <= 4'hd);
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// I prefix all of the registers (or wires) I use in formal
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// verification with f_, to distinguish them from the rest of the
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// project.
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reg f_valid_output;
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always @(*)
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begin
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// Determining if the output is valid or not is a rather
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// complex task--unusual for a typical assertion. Here, we'll
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// use f_valid_output and a series of _blocking_ statements
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// to determine if the output is one of our valid outputs.
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f_valid_output = 0;
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case(led_buf)
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8'h01: f_valid_output = 1'b1;
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8'h02: f_valid_output = 1'b1;
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8'h04: f_valid_output = 1'b1;
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8'h08: f_valid_output = 1'b1;
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8'h10: f_valid_output = 1'b1;
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8'h20: f_valid_output = 1'b1;
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8'h40: f_valid_output = 1'b1;
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8'h80: f_valid_output = 1'b1;
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endcase
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assert(f_valid_output);
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// SV supports a $onehot function which we could've also used
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// depending upon your version of Yosys. This function will
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// be true if one, and only one, bit in the argument is true.
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// Hence we might have said
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// assert($onehot(o_led));
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// and avoided this case statement entirely.
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end
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`endif
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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