115 lines
3.0 KiB
Verilog
115 lines
3.0 KiB
Verilog
`default_nettype none
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module top(i_clk, o_led, lcol1);
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parameter WIDTH = 22;
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input wire i_clk;
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output reg [7:0] o_led;
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output wire lcol1;
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wire clk_12MHz;
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clk_gen clk_gen_0 (/*autoinst*/
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// Outputs
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.o_clk (clk_12MHz),
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// Inputs
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.i_clk (i_clk));
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reg [WIDTH-1:0] counter;
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reg [7:0] obuf; // output buffer, take into account the icefun use active low LED
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reg [3:0] led_index;
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reg strobe;
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initial begin
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obuf = 8'h1;
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{strobe, counter} = 0;
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end
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always @(posedge clk_12MHz)
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{strobe, counter} <= counter + 1'b1;
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// fsm
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always @(posedge clk_12MHz) begin
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if (strobe) // led_index change only when strobe is 1
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if (led_index >= 4'hd)
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led_index <= 0;
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else
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led_index <= led_index + 1'b1;
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case (led_index)
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4'h0: obuf <= 8'h01;
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4'h1: obuf <= 8'h02;
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4'h2: obuf <= 8'h04;
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4'h3: obuf <= 8'h08;
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4'h4: obuf <= 8'h10;
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4'h5: obuf <= 8'h20;
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4'h6: obuf <= 8'h40;
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4'h7: obuf <= 8'h80;
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4'h8: obuf <= 8'h40;
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4'h9: obuf <= 8'h20;
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4'ha: obuf <= 8'h10;
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4'hb: obuf <= 8'h08;
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4'hc: obuf <= 8'h04;
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4'hd: obuf <= 8'h02;
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default : begin
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obuf <= 8'h01;
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end
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endcase
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end
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`ifdef FORMAL
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// led_index should never go beyond 13
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always @(*)
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assert(led_index <= 4'hd);
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// I prefix all of the registers (or wires) I use in formal
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// verification with f_, to distinguish them from the rest of the
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// project.
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reg f_valid_output;
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always @(*)
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begin
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// Determining if the output is valid or not is a rather
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// complex task--unusual for a typical assertion. Here, we'll
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// use f_valid_output and a series of _blocking_ statements
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// to determine if the output is one of our valid outputs.
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f_valid_output = 0;
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case(obuf)
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8'h01: f_valid_output = 1'b1;
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8'h02: f_valid_output = 1'b1;
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8'h04: f_valid_output = 1'b1;
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8'h08: f_valid_output = 1'b1;
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8'h10: f_valid_output = 1'b1;
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8'h20: f_valid_output = 1'b1;
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8'h40: f_valid_output = 1'b1;
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8'h80: f_valid_output = 1'b1;
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endcase
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assert(f_valid_output);
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// SV supports a $onehot function which we could've also used
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// depending upon your version of Yosys. This function will
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// be true if one, and only one, bit in the argument is true.
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// Hence we might have said
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// assert($onehot(o_led));
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// and avoided this case statement entirely.
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end
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`endif
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/* shift reg
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// shifting bit
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always @(posedge clk_12MHz)
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if (strobe)
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obuf <= {obuf[6:0], obuf[7]}; // left shift
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// obuf <= {obuf[0], obuf[7:1]}; // right shift
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*/
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always @(posedge clk_12MHz)
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o_led <= ~obuf;
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assign lcol1 = 1'b0;
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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