82 lines
1.9 KiB
Verilog
82 lines
1.9 KiB
Verilog
`default_nettype none
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module tdc #(parameter COUNTER_WIDTH=16)(
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input wire i_clk,
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input wire i_start,
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input wire i_stop,
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input wire i_reset,
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output wire o_ready,
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output wire [COUNTER_WIDTH-1:0] o_data
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);
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reg [COUNTER_WIDTH-1:0] counter;
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assign o_data = counter;
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// states
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localparam state_idle = 2'b00;
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localparam state_started = 2'b01;
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localparam state_running = 2'b10;
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localparam state_stopped = 2'b11;
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reg [1:0] current_state, next_state;
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// ensure that state changes each clock
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always @(posedge i_clk, posedge i_reset) begin
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if (i_reset) begin
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current_state <= state_idle;
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end else begin
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current_state <= next_state;
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end
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end
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// state logic
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/* verilator lint_off COMBDLY */
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always @(*) begin
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case (current_state)
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state_idle: begin
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if (i_start && (~i_stop))
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next_state <= state_started;
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else
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next_state <= state_idle;
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end
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state_started: begin
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if (~i_start && (~i_stop))
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next_state <= state_running;
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else
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next_state <= state_started;
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end
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state_running: begin
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if (~i_start && (i_stop))
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next_state <= state_stopped;
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else
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next_state <= state_running;
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end
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state_stopped: begin
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if (i_reset)
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next_state <= state_idle;
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else
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next_state <= state_stopped;
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end
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default : next_state <= current_state;
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endcase
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end
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/* verilator lint_on COMBDLY */
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// counter runs during running state only
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always @(posedge i_clk) begin
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case (current_state)
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state_idle: counter <= 0;
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state_started: counter <= 0;
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state_running: counter <= counter + 1;
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state_stopped: counter <= counter;
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default : counter <= 0;
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endcase
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end
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assign o_ready = (current_state == state_stopped);
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "./rtl" ".")
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// End:
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