57 lines
1.6 KiB
Makefile
57 lines
1.6 KiB
Makefile
SIM_TARGET = build/top
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BIN_TARGET = build/top.bin
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PCF = constraints/iceFUN.pcf
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TIMING = constraints/timing.py
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YOSYS = yosys
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PNR = nextpnr-ice40
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IPACK = icepack
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BURN = iceFUNprog
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VERILATOR=verilator
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VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
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VINC := $(VERILATOR_ROOT)/include
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RTL_SRC := $(wildcard rtl/*.v)
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SIM_SRC := $(wildcard sim/*.cc)
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BUILD_DIR := ./build
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.PHONY: all burn
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all: $(SIM_TARGET) $(BIN_TARGET)
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# -GWIDTH=5 allows passing parameter to verilog module
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$(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
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@echo "Running verilator"
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@mkdir -p $(BUILD_DIR)
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@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top\
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--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
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$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
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@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
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# std=c++11 flag is needed as of verilator v4.100
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$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
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@echo "Compiling simulation executable"
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@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
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$(VINC)/verilated_vcd_c.cpp $^ -o $@
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@echo "Run simulation with ./$(SIM_TARGET)"
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$(BUILD_DIR)/top.json: $(RTL_SRC)
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@echo "Synthesizing ..."
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@mkdir -p $(BUILD_DIR)
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@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^
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$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
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@echo "Routing and building binary stream ..."
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@$(PNR) -r --hx8k --json $< --package cb132 \
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--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
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--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q
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@$(IPACK) $(BUILD_DIR)/top.asc $@
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@echo "Done!"
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burn: $(BIN_TARGET)
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@$(BURN) $<
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.PHONY: clean
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clean:
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rm -rf $(BUILD_DIR)
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