104 lines
2.5 KiB
Verilog
104 lines
2.5 KiB
Verilog
`default_nettype none
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module uart_tx #(parameter CLOCKS_PER_BAUD=16'd868)(
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input wire clk,
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input wire rst_n,
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input wire en_i,
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input wire [7:0] data_i,
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output reg tx_o,
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output reg tx_done_o
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);
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localparam s_idle = 5'b00001,
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s_start = 5'b00010,
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s_wr = 5'b00100,
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s_stop = 5'b01000,
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s_done = 5'b10000;
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reg en_cnt;
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reg [15:0] cnt;
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reg [4:0] state;
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reg [7:0] data_r;
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reg [2:0] tx_bits;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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cnt <= 16'd0;
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else if ((en_cnt == 0) || (cnt == CLOCKS_PER_BAUD))
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cnt <= 16'd0;
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else
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cnt <= cnt + 1;
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end
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always @(posedge clk or negedge rst_n) begin
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if (~rst_n) begin
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state <= s_idle;
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tx_o <= 1;
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en_cnt <= 0;
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data_r <= 0;
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tx_bits <= 0;
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tx_done_o <= 0;
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end else begin
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case (state)
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s_idle: begin
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data_r <= data_i;
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tx_bits <= 0;
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tx_done_o <= 0;
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if (en_i == 1) begin
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en_cnt <= 1;
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state <= s_start;
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end else begin
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en_cnt <= 0;
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state <= s_idle;
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end
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end
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s_start: begin
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if (cnt == CLOCKS_PER_BAUD)
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state <= s_wr;
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else begin
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tx_o <= 0;
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state <= s_start;
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end
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end
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s_wr: begin
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if (cnt == CLOCKS_PER_BAUD) begin
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if (tx_bits == 3'd7)
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state <= s_stop;
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else begin
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tx_bits <= tx_bits + 1;
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state <= s_wr;
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end
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end else begin
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tx_o <= data_r[tx_bits];
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state <= s_wr;
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end
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end
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s_stop: begin
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if (cnt == CLOCKS_PER_BAUD)
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state <= s_done;
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else begin
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tx_o <= 1;
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state <= s_stop;
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end
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end
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s_done: begin
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en_cnt <= 0;
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tx_done_o <= 1;
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state <= s_idle;
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end
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default : begin
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state <= s_idle;
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end
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endcase
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end
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end
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endmodule
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// Local Variables:
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// verilog-library-directories:(".." "../rtl" ".")
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// End:
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