`default_nettype none
// dummy clock generator, should be replaced by a PLL clock gen eventually
module clk_gen #(parameter DIVISION=22)(
   input wire i_clk,
   output wire o_clk
);

reg [DIVISION-1:0] counter = 0;

always @(posedge i_clk) begin
   counter <= counter + 1;
end

assign o_clk = counter[DIVISION-1];

endmodule
// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: