`default_nettype none
module pos_edge_detector ( 
   input wire i_sig,            // Input signal for which positive edge has to be detected
   input wire i_clk,            // Input signal for clock
   output wire o_pe);           // Output signal that gives a pulse when a positive edge occurs

reg   sig_dly; // Internal signal to store the delayed version of signal

// This always block ensures that sig_dly is exactly 1 clock behind sig
always @ (posedge i_clk) begin
   sig_dly <= i_sig;
end

// Combinational logic where sig is AND with delayed, inverted version of sig
// Assign statement assigns the evaluated expression in the RHS to the internal net pe
assign o_pe = i_sig & ~sig_dly;            
endmodule