SIM_TARGET = build/top
BIN_TARGET = build/top.bin
PCF = iceFUN.pcf
YOSYS = yosys
PNR = nextpnr-ice40
IPACK = icepack
BURN = iceFUNprog

VERILATOR=verilator
VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
VINC := $(VERILATOR_ROOT)/include

RTL_SRC := $(wildcard rtl/*.v)
SIM_SRC := $(wildcard sim/*.cc)
BUILD_DIR := ./build

.PHONY: all burn
all: $(SIM_TARGET)  $(BIN_TARGET)

# -GWIDTH=5 allows passing parameter to verilog module
$(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
	@echo "Running verilator"
	@mkdir -p $(BUILD_DIR)
	@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top --Mdir $(BUILD_DIR)

$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
	@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk

# std=c++11 flag is needed as of verilator v4.100
$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
	@echo "Compiling simulation executable"
	@g++ -I$(VINC) -I$(BUILD_DIR) -std=c++14 $(VINC)/verilated.cpp\
		$(VINC)/verilated_vcd_c.cpp $^ -o $@
	@echo "Run simulation with ./$(SIM_TARGET)"

$(BUILD_DIR)/top.json: $(RTL_SRC)
	@echo "Synthesizing"
	@mkdir -p $(BUILD_DIR)
	@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $^

$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF)
	@echo "Routing and building binary stream"
	@$(PNR) -r --hx8k --json $< --package cb132 \
		--asc build/top.asc --opt-timing --pcf $(PCF) -q
	@$(IPACK) build/top.asc build/top.bin

burn: $(BIN_TARGET)
	@$(BURN) $<

.PHONY: clean
clean:
	rm -rf $(BUILD_DIR)