`default_nettype  none

module top(i_clk, o_led, lcol1);
   parameter WIDTH = 24;
   input wire i_clk;
   output wire o_led;
   output wire lcol1;

   wire clk_12MHz;

   clk_gen clk_gen_0 (/*autoinst*/
      // Outputs
      .o_clk                 (clk_12MHz),
      // Inputs
      .i_clk                 (i_clk));

   reg [WIDTH-1:0] counter;

   always @(posedge clk_12MHz)
      counter <= counter + 1'b1;

   assign o_led = counter[WIDTH-1];
   assign lcol1 = 1'b0;
endmodule

// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: