`default_nettype  none

module top #(parameter WIDTH=24)(
   input wire i_clk,
   input wire i_startN,
   input wire i_stopN,
   input wire i_resetN,
   output wire o_ledN,
   output wire o_readyN,
   output wire [5:0] o_dataN,
   output wire o_led_row_0
);
   wire clk_3Hz;
   wire clk_100MHz;
   reg buf_led = 0;
   wire buf_ready;
   wire [5:0] buf_data;
   assign o_readyN = ~buf_ready;
   assign o_dataN = ~buf_data;

/* verilator lint_off PINMISSING */
   clk_gen #(.DIVISION(22)) clk_gen0 (
                      .o_div_clk        (clk_3Hz),
                      .o_clk_100MHz (clk_100MHz),
                      .i_clk            (i_clk));
/* verilator lint_on PINMISSING */

   tdc #(.COUNTER_WIDTH(6)) tdc0 (
            // Outputs
            .o_ready                    (buf_ready),
            .o_data                     (buf_data),
            // Inputs
            .i_clk                      (clk_100MHz),
            .i_start                    (~i_startN),
            .i_stop                     (~i_stopN),
            .i_reset                   (~i_resetN));

   always @(posedge clk_3Hz) begin
      buf_led <= ~buf_led;
   end

   assign o_ledN = ~buf_led;
   assign o_led_row_0 = 1'b0;
endmodule

// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: