`default_nettype  none

module top(i_clk,
   i_cyc, i_stb, i_we, i_addr, i_data,
   o_stall, o_ack, o_data,
   o_led, o_led_row_0);
input	wire		i_clk;
//
// Our wishbone bus interface
input	wire		i_cyc, i_stb, i_we;
input	wire		i_addr;
input	wire	[31:0]	i_data;
//
output	wire		o_stall;
output	reg		o_ack;
output	wire	[31:0]	o_data;
//
// The output LED
output wire o_led_row_0;
output	reg	[5:0]	o_led;

wire		busy;
reg	[3:0]	state;

initial	state = 0;
always @(posedge i_clk) begin
   if ((i_stb)&&(i_we)&&(!o_stall))
      state <= 4'h1;
   else if (state >= 4'd11)
      state <= 4'h0;
   else if (state != 0)
      state <= state + 1'b1;
end

always @(posedge i_clk) begin
   case(state)
      4'h1: o_led <= 6'b00_0001;
      4'h2: o_led <= 6'b00_0010;
      4'h3: o_led <= 6'b00_0100;
      4'h4: o_led <= 6'b00_1000;
      4'h5: o_led <= 6'b01_0000;
      4'h6: o_led <= 6'b10_0000;
      4'h7: o_led <= 6'b01_0000;
      4'h8: o_led <= 6'b00_1000;
      4'h9: o_led <= 6'b00_0100;
      4'ha: o_led <= 6'b00_0010;
      4'hb: o_led <= 6'b00_0001;
      default: o_led <= 6'b00_0000;
   endcase
end

assign	busy = (state != 0);

initial	o_ack = 1'b0;
always @(posedge i_clk)
   o_ack <= (i_stb)&&(!o_stall);

assign	o_stall = (busy)&&(i_we);
assign	o_data = { 28'h0, state };
assign o_led_row_0 = 0;

// Verilator lint_off UNUSED
wire	[33:0]	unused;
assign	unused = { i_cyc, i_addr, i_data };
// Verilator lint_on  UNUSED
//
endmodule
// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: