`default_nettype  none

/* verilator lint_off UNUSED */
module top #(parameter WIDTH=24)(
   input wire i_clk,
   input wire i_startN,
   input wire i_stopN,
   input wire i_resetN,
   // input wire [31:0] i_calib_delay,
   output wire o_ledN,
   output wire o_readyN,
   output wire [5:0] o_dataN,
   output wire o_led_row_0,
   output wire o_uart_tx
);
   wire clk_1Hz; // 1.4 Hz actually
   wire clk_100MHz;
   reg buf_led = 0;
   wire buf_ready;
   parameter TDC_COUNTER_WIDTH = 32;
   wire [TDC_COUNTER_WIDTH-1:0] buf_data;
   assign o_readyN = ~buf_ready;
   assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];

   /* verilator lint_off PINMISSING */
   clk_gen #(.DIVISION(26)) clk_gen0 (
   .o_div_clk        (clk_1Hz),
   .o_clk_100MHz (clk_100MHz),
   .i_clk            (i_clk));
   /* verilator lint_on PINMISSING */
   reg db_start, db_stop;
   reg [31:0] cal_delay = 15000;
   wire aa;
   debounce db1 (
      .db                       (aa),
      .clk                      (clk_100MHz),
      .reset                    (~i_resetN),
      .sw                       (~i_startN ));
   tdc_calib tcalib (
      .o_calib_start     (db_start),
      .o_calib_stop      (db_stop),
      .i_clk             (i_clk),
      // .i_delay           (i_calib_delay),
      .i_delay           (cal_delay),
      .i_start_btn       (aa),
      .i_resetN          (i_resetN)
   );
   // always @(posedge clk_100MHz) begin
      // db_start <= ~i_startN;
      // db_stop <= ~i_stopN;
   // end
`ifdef DEBOUNCE
   debounce db1 (
      // Outputs
      .db                       (db_start),
      // Inputs
      .clk                      (clk_100MHz),
      .reset                    (~i_resetN),
      .sw                       (~i_startN));
   debounce db2 (
      // Outputs
      .db                       (db_stop),
      // Inputs
      .clk                      (clk_100MHz),
      .reset                    (~i_resetN),
      .sw                       (~i_stopN));
`endif

   tdc #(.COUNTER_WIDTH(32)) tdc0 (
   // Outputs
   .o_ready                    (buf_ready),
   .o_data                     (buf_data),
   // Inputs
   .i_clk                      (clk_100MHz),
   .i_start                    (db_start),
   .i_stop                     (db_stop),
   .i_reset                   (~i_resetN));

   always @(posedge clk_1Hz) begin
      buf_led <= ~buf_led;
   end

   assign o_ledN = ~buf_led;
   assign o_led_row_0 = 1'b0;

   parameter    CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
   parameter    BAUD_RATE = 115_200; // 115.2 KBaud
   parameter    INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);

   // transferring data out every second
   wire tx_start;
   pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start));

   wire         tx_busy;
   reg          tx_stb;
   reg  [2:0]   tx_index;
   reg  [7:0]   tx_data;

   // there are 4bytes to transmit
   initial      tx_index = 3'd0;
   always @(posedge clk_100MHz) begin
      if ((tx_stb)&&(!tx_busy))
         tx_index <= tx_index + 1'b1;
   end
   always @(posedge clk_100MHz) begin
      case(tx_index)
         3'd0: tx_data <= "f";
         3'd1: tx_data <= "f";
         3'd2: tx_data <= buf_data[31:24];
         3'd3: tx_data <= buf_data[23:16];
         3'd4: tx_data <= buf_data[15:8];
         3'd5: tx_data <= buf_data[7:0];
         3'd6: tx_data <= "f";
         3'd7: tx_data <= "f";
      endcase
   end
   initial      tx_stb = 1'b0;
   // transmit only when data is ready
   always @(posedge clk_100MHz) begin
      if (tx_start)
         tx_stb <= 1'b1;
      else if ((tx_stb)&&(!tx_busy)&&(tx_index==3'd7))
         tx_stb <= 1'b0;
   end

   txuart #(INITIAL_UART_SETUP[23:0]) transmitter(clk_100MHz,
      tx_stb, tx_data, o_uart_tx, tx_busy);

endmodule

// Local Variables:
// verilog-library-directories:(".." "./rtl" ".")
// End: