`default_nettype  none

module blinky(o_led, lcol1, sysclk);
   parameter WIDTH = 24;
   
   output wire o_led;
   output wire lcol1;
   input wire sysclk;
   wire clk_100MHz;
   wire locked;

   pll_100MHz pll_0 (.clock_in(sysclk), .clock_out(clk_100MHz), .locked(locked));

   reg [WIDTH-1:0] counter;

   always @(posedge clk_100MHz)
      counter <= counter + 1'b1;

   assign o_led = counter[WIDTH-1];
   assign lcol1 = 1'b0;
endmodule