From e7a23afcb01056e0a537d5e0bbe7c1ed390e2921 Mon Sep 17 00:00:00 2001
From: Nam Tran <thnam.me@gmail.com>
Date: Mon, 2 Nov 2020 15:49:11 -0600
Subject: [PATCH] use 3-bit transmit state, add header/footer around data, skip
 debounce for now

---
 tdc/rtl/top.v  | 30 ++++++++++++++----------------
 tdc/sim/top.cc |  2 ++
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v
index 4113f0b..61aaa70 100644
--- a/tdc/rtl/top.v
+++ b/tdc/rtl/top.v
@@ -27,13 +27,11 @@ module top #(parameter WIDTH=24)(
    .i_clk            (i_clk));
    /* verilator lint_on PINMISSING */
    reg db_start, db_stop;
-   // skipping the debouncing in simulation
-`ifdef VERILATOR
    always @(posedge clk_100MHz) begin
       db_start <= ~i_startN;
       db_stop <= ~i_stopN;
    end
-`else
+`ifdef DEBOUNCE
    debounce db1 (
       // Outputs
       .db                       (db_start),
@@ -50,7 +48,7 @@ module top #(parameter WIDTH=24)(
       .sw                       (~i_stopN));
 `endif
 
-   tdc #(.COUNTER_WIDTH(TDC_COUNTER_WIDTH)) tdc0 (
+   tdc #(.COUNTER_WIDTH(32)) tdc0 (
    // Outputs
    .o_ready                    (buf_ready),
    .o_data                     (buf_data),
@@ -81,21 +79,21 @@ module top #(parameter WIDTH=24)(
    reg	[7:0]	tx_data;
 
    // there are 4bytes to transmit
-   initial	tx_index = 3'h0;
+   initial	tx_index = 3'd0;
    always @(posedge clk_100MHz) begin
-      if ((tx_stb)&&(!tx_busy)) begin
-         if (tx_index < 3'd4)
-            tx_index <= tx_index + 1'b1;
-         else
-            tx_index <= 0;
-      end
+      if ((tx_stb)&&(!tx_busy))
+         tx_index <= tx_index + 1'b1;
    end
    always @(posedge clk_100MHz) begin
       case(tx_index)
-         3'd1: tx_data <= buf_data[31:24];
-         3'd2: tx_data <= buf_data[23:16];
-         3'd3: tx_data <= buf_data[15:8];
-         3'd4: tx_data <= buf_data[7:0];
+         3'd0: tx_data <= "f";
+         3'd1: tx_data <= "f";
+         3'd2: tx_data <= buf_data[31:24];
+         3'd3: tx_data <= buf_data[23:16];
+         3'd4: tx_data <= buf_data[15:8];
+         3'd5: tx_data <= buf_data[7:0];
+         3'd6: tx_data <= "f";
+         3'd7: tx_data <= "f";
       endcase
    end
    initial	tx_stb = 1'b0;
@@ -103,7 +101,7 @@ module top #(parameter WIDTH=24)(
    always @(posedge clk_100MHz) begin
       if (tx_start)
          tx_stb <= 1'b1;
-      else if ((tx_stb)&&(!tx_busy)&&(tx_index==3'd4))
+      else if ((tx_stb)&&(!tx_busy)&&(tx_index==3'd7))
          tx_stb <= 1'b0;
    end
 
diff --git a/tdc/sim/top.cc b/tdc/sim/top.cc
index c268a07..7746a8c 100644
--- a/tdc/sim/top.cc
+++ b/tdc/sim/top.cc
@@ -61,6 +61,8 @@ int main(int argc, char **argv) {
 
    for (int k = 0; k < 394; k++) 
       tick(++tickcount, tb, tfp);
+   for (int k = 0; k < (1<<17); k++) 
+      tick(++tickcount, tb, tfp);
 
    // stop pulse
    tb->i_stopN = 0;