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hack to use PLL in synthesizing, and fake 100 MHz on verilator

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Nam Tran
2020-10-26 21:58:13 -05:00
parent f36bb84065
commit 61bab9153d
3 changed files with 67 additions and 13 deletions
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14
tdc/rtl/top.v
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@@ -11,24 +11,26 @@ module top #(parameter WIDTH=24)(
output wire o_led_row_0
);
wire clk_3Hz;
wire clk_100MHz;
reg buf_led = 0;
wire buf_ready;
wire [5:0] buf_data;
assign o_readyN = ~buf_ready;
assign o_dataN = ~buf_data;
clk_gen #(.DIVISION(22)) clk_gen0 (/*autoinst*/
// Outputs
.o_clk (clk_3Hz),
// Inputs
/* verilator lint_off PINMISSING */
clk_gen #(.DIVISION(22)) clk_gen0 (
.o_div_clk (clk_3Hz),
.o_clk_100MHz (clk_100MHz),
.i_clk (i_clk));
/* verilator lint_on PINMISSING */
tdc #(.COUNTER_WIDTH(6)) tdc0 (/*autoinst*/
tdc #(.COUNTER_WIDTH(6)) tdc0 (
// Outputs
.o_ready (buf_ready),
.o_data (buf_data),
// Inputs
.i_clk (clk_3Hz),
.i_clk (clk_100MHz),
.i_start (~i_startN),
.i_stop (~i_stopN),
.i_reset (~i_resetN));