formal verification stuff

fsm/Makefile

@@ -6,6 +6,7 @@ YOSYS = yosys
 PNR = nextpnr-ice40
 IPACK = icepack
 BURN = iceFUNprog
+SBY = sby
 
 VERILATOR=verilator
 VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
@@ -13,9 +14,11 @@ VINC := $(VERILATOR_ROOT)/include
 
 RTL_SRC := $(wildcard rtl/*.v)
 SIM_SRC := $(wildcard sim/*.cc)
+FV_SRC := sim/top.sby
+
 BUILD_DIR := ./build
 
-.PHONY: all burn
+.PHONY: all burn fv clean
 all: $(SIM_TARGET)  $(BIN_TARGET)
 
 # -GWIDTH=5 allows passing parameter to verilog module
@@ -51,6 +54,8 @@ $(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
 burn: $(BIN_TARGET)
 	@$(BURN) $<
 
-.PHONY: clean
+fv:
+	@$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
+
 clean:
 	rm -rf $(BUILD_DIR)