can transmit data out, but in wrong order ...
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141
tdc/rtl/txuart.v
Normal file
141
tdc/rtl/txuart.v
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`default_nettype none
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module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy);
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parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
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input wire i_clk;
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input wire i_wr;
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input wire [7:0] i_data;
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// And the UART output line itself
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output wire o_uart_tx;
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// A line to tell others when we are ready to accept data. If
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// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
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// for transmission.
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output reg o_busy;
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// Define several states
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localparam [3:0] START = 4'h0,
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BIT_ZERO = 4'h1,
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BIT_ONE = 4'h2,
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BIT_TWO = 4'h3,
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BIT_THREE = 4'h4,
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BIT_FOUR = 4'h5,
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BIT_FIVE = 4'h6,
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BIT_SIX = 4'h7,
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BIT_SEVEN = 4'h8,
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LAST = 4'h8,
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IDLE = 4'hf;
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reg [23:0] counter;
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reg [3:0] state;
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reg [8:0] lcl_data;
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reg baud_stb;
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// o_busy
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//
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// This is a register, designed to be true is we are ever busy above.
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// originally, this was going to be true if we were ever not in the
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// idle state. The logic has since become more complex, hence we have
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// a register dedicated to this and just copy out that registers value.
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initial o_busy = 1'b0;
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initial state = IDLE;
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always @(posedge i_clk)
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if ((i_wr)&&(!o_busy))
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// Immediately start us off with a start bit
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{ o_busy, state } <= { 1'b1, START };
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else if (baud_stb)
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begin
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if (state == IDLE) // Stay in IDLE
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{ o_busy, state } <= { 1'b0, IDLE };
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else if (state < LAST) begin
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o_busy <= 1'b1;
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state <= state + 1'b1;
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end else // Wait for IDLE
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{ o_busy, state } <= { 1'b1, IDLE };
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end
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// lcl_data
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//
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// This is our working copy of the i_data register which we use
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// when transmitting. It is only of interest during transmit, and is
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// allowed to be whatever at any other time. Hence, if o_busy isn't
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// true, we can always set it. On the one clock where o_busy isn't
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// true and i_wr is, we set it and o_busy is true thereafter.
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// Then, on any baud_stb (i.e. change between baud intervals)
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// we simple logically shift the register right to grab the next bit.
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initial lcl_data = 9'h1ff;
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always @(posedge i_clk)
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if ((i_wr)&&(!o_busy))
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lcl_data <= { i_data, 1'b0 };
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else if (baud_stb)
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lcl_data <= { 1'b1, lcl_data[8:1] };
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// o_uart_tx
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//
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// This is the final result/output desired of this core. It's all
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// centered about o_uart_tx. This is what finally needs to follow
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// the UART protocol.
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//
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assign o_uart_tx = lcl_data[0];
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// All of the above logic is driven by the baud counter. Bits must last
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// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
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// make certain of that.
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//
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// The basic logic is this: at the beginning of a bit interval, start
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// the baud counter and set it to count CLOCKS_PER_BAUD. When it gets
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// to zero, restart it.
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//
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// However, comparing a 28'bit number to zero can be rather complex--
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// especially if we wish to do anything else on that same clock. For
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// that reason, we create "baud_stb". baud_stb is
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// nothing more than a flag that is true anytime baud_counter is zero.
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// It's true when the logic (above) needs to step to the next bit.
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// Simple enough?
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//
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// I wish we could stop there, but there are some other (ugly)
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// conditions to deal with that offer exceptions to this basic logic.
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//
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// 1. When the user has commanded a BREAK across the line, we need to
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// wait several baud intervals following the break before we start
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// transmitting, to give any receiver a chance to recognize that we are
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// out of the break condition, and to know that the next bit will be
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// a stop bit.
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//
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// 2. A reset is similar to a break condition--on both we wait several
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// baud intervals before allowing a start bit.
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//
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// 3. In the idle state, we stop our counter--so that upon a request
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// to transmit when idle we can start transmitting immediately, rather
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// than waiting for the end of the next (fictitious and arbitrary) baud
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// interval.
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//
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// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
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// the idle state, but we also just accepted a command to start writing
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// the next word. At this point, the baud counter needs to be reset
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// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
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//
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// The logic is a bit twisted here, in that it will only check for the
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// above condition when baud_stb is false--so as to make
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// certain the STOP bit is complete.
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initial baud_stb = 1'b1;
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initial counter = 0;
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always @(posedge i_clk)
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if ((i_wr)&&(!o_busy))
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begin
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counter <= CLOCKS_PER_BAUD - 1'b1;
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baud_stb <= 1'b0;
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end else if (!baud_stb)
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begin
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baud_stb <= (counter == 24'h01);
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counter <= counter - 1'b1;
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end else if (state != IDLE)
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begin
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counter <= CLOCKS_PER_BAUD - 1'b1;
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baud_stb <= 1'b0;
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end
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endmodule
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