nam/iceFun_Projects
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

can transmit data out, but in wrong order ...

Browse Source
This commit is contained in:
Nam Tran
2020-11-01 09:30:46 -06:00
parent aeaf18c2d4
commit 45f845f671
5 changed files with 209 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
tdc/rtl/top.v
View File

@@ -8,18 +8,17 @@ module top #(parameter WIDTH=24)(
output wire o_ledN,
output wire o_readyN,
output wire [5:0] o_dataN,
output wire o_led_row_0
output wire o_led_row_0,
output wire o_uart_tx
);
wire clk_1Hz; // 1.4 Hz actually
wire clk_100MHz;
reg buf_led = 0;
wire buf_ready;
/* verilator lint_off UNUSED */
parameter TDC_COUNTER_WIDTH = 28;
parameter TDC_COUNTER_WIDTH = 32;
wire [TDC_COUNTER_WIDTH-1:0] buf_data;
assign o_readyN = ~buf_ready;
assign o_dataN = ~buf_data[TDC_COUNTER_WIDTH-1:TDC_COUNTER_WIDTH-6];
/* verilator lint_on UNUSED */
/* verilator lint_off PINMISSING */
clk_gen #(.DIVISION(26)) clk_gen0 (
@@ -28,6 +27,7 @@ module top #(parameter WIDTH=24)(
.i_clk (i_clk));
/* verilator lint_on PINMISSING */
reg db_start, db_stop;
// skipping the debouncing in simulation
`ifdef VERILATOR
always @(posedge clk_100MHz) begin
db_start <= ~i_startN;
@@ -66,6 +66,50 @@ module top #(parameter WIDTH=24)(
assign o_ledN = ~buf_led;
assign o_led_row_0 = 1'b0;
parameter CLOCK_RATE_HZ = 100_000_000; // 100MHz clock
parameter BAUD_RATE = 115_200; // 115.2 KBaud
parameter INITIAL_UART_SETUP = (CLOCK_RATE_HZ/BAUD_RATE);
// transferring data out every second
wire tx_start;
pos_edge_detector pe0(.i_sig(buf_ready), .i_clk(clk_100MHz), .o_pe(tx_start));
wire tx_busy;
reg tx_stb;
reg [2:0] tx_index;
reg [7:0] tx_data;
// there are 4bytes to transmit
initial tx_index = 3'h0;
always @(posedge clk_100MHz) begin
if ((tx_stb)&&(!tx_busy)) begin
if (tx_index < 3'd4)
tx_index <= tx_index + 1'b1;
else
tx_index <= 0;
end
end
always @(posedge clk_100MHz) begin
case(tx_index)
3'd1: tx_data <= buf_data[31:24];
3'd2: tx_data <= buf_data[23:16];
3'd3: tx_data <= buf_data[15:8];
3'd4: tx_data <= buf_data[7:0];
endcase
end
initial tx_stb = 1'b0;
// transmit only when data is ready
always @(posedge clk_100MHz) begin
if (tx_start)
tx_stb <= 1'b1;
else if ((tx_stb)&&(!tx_busy)&&(tx_index==3'd4))
tx_stb <= 1'b0;
end
txuart #(INITIAL_UART_SETUP[23:0]) transmitter(clk_100MHz,
tx_stb, tx_data, o_uart_tx, tx_busy);
endmodule
// Local Variables: