add tut3 folder, shift register code works

fsm/rtl/clk_gen.v

@@ -0,0 +1,13 @@
+`default_nettype none
+// dummy clock generator, should be replaced by a PLL clock gen eventually
+module clk_gen(
+   input wire i_clk,
+   output wire o_clk
+);
+
+assign o_clk = i_clk;
+
+endmodule
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End:

fsm/rtl/top.v

@@ -0,0 +1,42 @@
+`default_nettype  none
+
+module top(i_clk, o_led, lcol1);
+   parameter WIDTH = 22;
+   input wire i_clk;
+   output reg [7:0] o_led;
+   output wire lcol1;
+
+   wire clk_12MHz;
+
+   clk_gen clk_gen_0 (/*autoinst*/
+      // Outputs
+      .o_clk                 (clk_12MHz),
+      // Inputs
+      .i_clk                 (i_clk));
+
+   reg [WIDTH-1:0] counter;
+   reg [7:0] obuf; // output buffer, take into account the icefun use active low LED
+   reg strobe;
+
+   initial begin
+      obuf = 8'h1;
+      {strobe, counter} = 0;
+   end
+
+   always @(posedge clk_12MHz)
+      {strobe, counter} <= counter + 1'b1;
+
+   // shifting bit, to the left
+   always @(posedge clk_12MHz)
+      if (strobe)
+         obuf <= {obuf[6:0], obuf[7]};
+
+   always @(*)
+      o_led = ~obuf;
+
+   assign lcol1 = 1'b0;
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".." "./rtl" ".")
+// End: