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timescale in verilator command

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Nam Tran
2020-10-23 10:16:04 -05:00
parent f9b7340667
commit 42c5b8a47f
1 changed files with 2 additions and 1 deletions
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3
tdc/Makefile
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@@ -21,7 +21,8 @@ all: $(SIM_TARGET) $(BIN_TARGET)
$(BUILD_DIR)/Vtop.cc: $(RTL_SRC) $(BUILD_DIR)/Vtop.cc: $(RTL_SRC)
@echo "Running verilator" @echo "Running verilator"
@mkdir -p $(BUILD_DIR) @mkdir -p $(BUILD_DIR)
@$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top --Mdir $(BUILD_DIR) @$(VERILATOR) --trace -Wall -GWIDTH=10 -cc $^ --top-module top\
--Mdir $(BUILD_DIR) --timescale-override 10ns/1ns
$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc $(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cc
@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk @make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk