another uart demonstration: uart echo module

uart/Makefile

@@ -0,0 +1,56 @@
+# Project setup
+TOP ?= top
+SIM = iverilog
+WAVE = vvp
+
+PCF = constraints/iceFUN.pcf
+TIMING = constraints/timing.py
+YOSYS = yosys
+PNR = nextpnr-ice40
+IPACK = icepack
+BURN = iceFUNprog
+SBY = sby
+
+BUILD_DIR = ./build
+VCD = $(BUILD_DIR)/waveform.vcd
+BIN_TARGET = build/top.bin
+
+# Files
+MODULES += $(wildcard rtl/*.v)
+TEST = tb.v
+
+define colorecho
+      @tput setaf 6
+      @echo $1
+      @tput sgr0
+endef
+
+.PHONY: all clean burn
+
+all: sim
+
+sim: $(TEST) $(MODULES)
+	@mkdir -p $(BUILD_DIR)
+	@$(SIM) -o $(BUILD_DIR)/tb_out $< $(MODULES) && $(WAVE) $(BUILD_DIR)/tb_out && open $(VCD)
+
+$(BUILD_DIR)/top.json: $(MODULES)
+	$(call colorecho, "Synthesizing ...")
+	mkdir -p $(BUILD_DIR)
+	$(YOSYS) -p "synth_ice40 -top uart_echo -json build/top.json" -q $^
+
+$(BIN_TARGET): $(BUILD_DIR)/top.json $(PCF) $(TIMING)
+	$(call colorecho, "Routing and building binary stream ...") 
+	$(PNR) -r --hx8k --json $< --package cb132 \
+		--asc $(BUILD_DIR)/top.asc --opt-timing --pcf $(PCF) \
+		--pre-pack $(TIMING) -l $(BUILD_DIR)/pnr_report.txt -q 
+	$(IPACK) $(BUILD_DIR)/top.asc $@
+	$(call colorecho, "Done!")
+
+burn: $(BIN_TARGET)
+	$(BURN) $<
+
+fv:
+	$(SBY) -f $(FV_SRC) -d $(BUILD_DIR)/fv
+
+clean:
+	rm -rf $(BUILD_DIR)