From 1198429d53ee1603df1b4260bba50506cce6eb96 Mon Sep 17 00:00:00 2001
From: Nam Tran <thnam.me@gmail.com>
Date: Thu, 22 Oct 2020 21:28:17 -0500
Subject: [PATCH] new project for tdc, copied code from blinky and changed
 structure

---
 tdc/Makefile    | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 tdc/iceFUN.pcf  |  5 +++++
 tdc/rtl/top.v   | 17 +++++++++++++++++
 tdc/sim/top.cpp | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 117 insertions(+)
 create mode 100644 tdc/Makefile
 create mode 100644 tdc/iceFUN.pcf
 create mode 100644 tdc/rtl/top.v
 create mode 100644 tdc/sim/top.cpp

diff --git a/tdc/Makefile b/tdc/Makefile
new file mode 100644
index 0000000..02676f8
--- /dev/null
+++ b/tdc/Makefile
@@ -0,0 +1,48 @@
+SIM_TARGET = build/top
+BIN_TARGET = build/top.bin
+PCF = iceFUN.pcf
+YOSYS = yosys
+PNR = nextpnr-ice40
+IPACK = icepack
+BURN = iceFUNprog
+
+VERILATOR=verilator
+VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
+VINC := $(VERILATOR_ROOT)/include
+
+RTL_SRC := $(wildcard rtl/*.v)
+SIM_SRC := $(wildcard sim/*.cpp)
+BUILD_DIR := ./build
+
+.PHONY: all burn
+all: $(SIM_TARGET)  $(BIN_TARGET)
+
+# -GWIDTH=5 allows passing parameter to verilog module
+$(BUILD_DIR)/Vtop.cpp: $(RTL_SRC)
+	@echo "Running verilator"
+	@mkdir -p $(BUILD_DIR)
+	@$(VERILATOR) --trace -Wall -GWIDTH=20 -cc $^ --top-module top --Mdir $(BUILD_DIR)
+
+$(BUILD_DIR)/Vtop__ALL.a: $(BUILD_DIR)/Vtop.cpp
+	@make --no-print-directory -C $(BUILD_DIR) -f Vtop.mk
+
+# std=c++11 flag is needed from verilator v4.100
+$(SIM_TARGET): $(SIM_SRC) $(BUILD_DIR)/Vtop__ALL.a
+	@echo "Compiling simulation executable"
+	g++ -I$(VINC) -I$(BUILD_DIR) -std=c++11 $(VINC)/verilated.cpp\
+		$(VINC)/verilated_vcd_c.cpp $^ -o $@
+	@echo "Run simulation with ./$(TARGET)"
+
+$(BIN_TARGET): $(RTL_SRC) $(PCF)
+	@echo "Building binary stream"
+	@$(YOSYS) -p "synth_ice40 -top top -json build/top.json" -q $<
+	@$(PNR) -r --hx8k --json build/top.json --package cb132 \
+		--asc build/top.asc --opt-timing --pcf $(PCF) -q
+	@$(IPACK) build/top.asc build/top.bin
+
+burn: $(BIN_TARGET)
+	@$(BURN) $<
+
+.PHONY: clean
+clean:
+	rm -rf $(BUILD_DIR)
diff --git a/tdc/iceFUN.pcf b/tdc/iceFUN.pcf
new file mode 100644
index 0000000..c84781b
--- /dev/null
+++ b/tdc/iceFUN.pcf
@@ -0,0 +1,5 @@
+# For iceFUN board
+
+set_io --warn-no-port o_led 	C10
+set_io --warn-no-port i_clk  	P7
+set_io --warn-no-port lcol1	A12
diff --git a/tdc/rtl/top.v b/tdc/rtl/top.v
new file mode 100644
index 0000000..c0febf9
--- /dev/null
+++ b/tdc/rtl/top.v
@@ -0,0 +1,17 @@
+`default_nettype  none
+
+module top(i_clk, o_led, lcol1);
+   parameter WIDTH = 24;
+   input wire i_clk;
+   output wire o_led;
+   output wire lcol1;
+
+   reg [WIDTH-1:0] counter;
+
+   always @(posedge i_clk)
+      counter <= counter + 1'b1;
+
+   assign o_led = counter[WIDTH-1];
+   assign lcol1 = 1'b0;
+endmodule
+
diff --git a/tdc/sim/top.cpp b/tdc/sim/top.cpp
new file mode 100644
index 0000000..fb97897
--- /dev/null
+++ b/tdc/sim/top.cpp
@@ -0,0 +1,47 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+#include "Vtop.h"
+
+void	tick(int tickcount, Vtop *tb, VerilatedVcdC* tfp) {
+	tb->eval();
+	if (tfp)
+		tfp->dump(tickcount * 10 - 2);
+	tb->i_clk = 1;
+	tb->eval();
+	if (tfp)
+		tfp->dump(tickcount * 10);
+	tb->i_clk = 0;
+	tb->eval();
+	if (tfp) {
+		tfp->dump(tickcount * 10 + 5);
+		tfp->flush();
+	}
+}
+
+int main(int argc, char **argv) {
+	// Call commandArgs first!
+	Verilated::commandArgs(argc, argv);
+
+	// Instantiate our design
+	Vtop *tb = new Vtop;
+	Verilated::traceEverOn(true);
+	VerilatedVcdC* tfp = new VerilatedVcdC;
+
+	tb->trace(tfp, 00);
+	tfp->open("build/waveform.vcd");
+
+	unsigned tickcount = 0;
+  int last_led = tb->o_led;
+
+	for(int k=0; k<(1 << 23); k++) {
+    tick(++tickcount, tb, tfp);
+
+    if (last_led != tb->o_led) {
+      printf("k = %7d, led = %d\n", k, tb->o_led);
+    }
+
+    last_led = tb->o_led;
+	}
+}