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initial 5640 support

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This commit is contained in:
me-no-dev
2020-02-25 01:05:01 +02:00
parent a4f6d924ce
commit ae32d52cc2
20 changed files with 2189 additions and 239 deletions
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231
sensors/ov2640.c
View File

@@ -133,127 +133,57 @@ static int set_pixformat(sensor_t *sensor, pixformat_t pixformat)
return ret;
}
//Functions are not needed currently
#if 0
//Set the sensor output window
int set_output_window(sensor_t *sensor, uint16_t x, uint16_t y, uint16_t width, uint16_t height)
{
static int set_window(sensor_t *sensor, ov2640_sensor_mode_t mode, int offset_x, int offset_y, int max_x, int max_y, int w, int h){
int ret = 0;
uint16_t endx, endy;
uint8_t com1, reg32;
endy = y + height / 2;
com1 = read_reg(sensor, BANK_SENSOR, COM1);
WRITE_REG_OR_RETURN(BANK_SENSOR, COM1, (com1 & 0XF0) | (((endy & 0X03) << 2) | (y & 0X03)));
WRITE_REG_OR_RETURN(BANK_SENSOR, VSTART, y >> 2);
WRITE_REG_OR_RETURN(BANK_SENSOR, VSTOP, endy >> 2);
endx = x + width / 2;
reg32 = read_reg(sensor, BANK_SENSOR, REG32);
WRITE_REG_OR_RETURN(BANK_SENSOR, REG32, (reg32 & 0XC0) | (((endx & 0X07) << 3) | (x & 0X07)));
WRITE_REG_OR_RETURN(BANK_SENSOR, HSTART, x >> 3);
WRITE_REG_OR_RETURN(BANK_SENSOR, HSTOP, endx >> 3);
return ret;
}
// Set the image output size (final output resolution)
int set_output_size(sensor_t *sensor, uint16_t width, uint16_t height)
{
int ret = 0;
uint16_t h, w;
if(width % 4) {
return -1;
}
if(height % 4 ) {
return -2;
}
w = width / 4;
h = height / 4;
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, RESET_DVP);
WRITE_REG_OR_RETURN(BANK_DSP, ZMOW, w & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, ZMOH, h & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, ZMHH, ((w >> 8) & 0X03) | ((h >> 6) & 0X04));
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0X00);
return ret;
}
//Set the image window size >= output size
int set_window_size(sensor_t *sensor, uint16_t x, uint16_t y, uint16_t width, uint16_t height)
{
int ret = 0;
uint16_t w, h;
if(width % 4) {
return -1;
}
if(height % 4) {
return -2;
}
w = width / 4;
h = height / 4;
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, RESET_DVP);
WRITE_REG_OR_RETURN(BANK_DSP, HSIZE, w & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, VSIZE, h & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, XOFFL, x & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, YOFFL, y & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, VHYX, ((h >> 1) & 0X80) | ((y >> 4) & 0X70) | ((w >> 5) & 0X08) | ((x >> 8) & 0X07));
WRITE_REG_OR_RETURN(BANK_DSP, TEST, (w >> 2) & 0X80);
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0X00);
return ret;
}
//Set the sensor resolution (UXGA, SVGA, CIF)
int set_image_size(sensor_t *sensor, uint16_t width, uint16_t height)
{
int ret = 0;
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, RESET_DVP);
WRITE_REG_OR_RETURN(BANK_DSP, HSIZE8, (width >> 3) & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, VSIZE8, (height >> 3) & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, SIZEL, ((width & 0X07) << 3) | ((width >> 4) & 0X80) | (height & 0X07));
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0X00);
return ret;
}
#endif
static int set_framesize(sensor_t *sensor, framesize_t framesize)
{
int ret = 0;
uint16_t w = resolution[framesize][0];
uint16_t h = resolution[framesize][1];
const uint8_t (*regs)[2];
ov2640_clk_t c;
c.reserved = 0;
sensor->status.framesize = framesize;
max_x /= 4;
max_y /= 4;
w /= 4;
h /= 4;
uint8_t win_regs[][2] = {
{BANK_SEL, BANK_DSP},
{HSIZE, max_x & 0xFF},
{VSIZE, max_y & 0xFF},
{XOFFL, offset_x & 0xFF},
{YOFFL, offset_y & 0xFF},
{VHYX, ((max_y >> 1) & 0X80) | ((offset_y >> 4) & 0X70) | ((max_x >> 5) & 0X08) | ((offset_y >> 8) & 0X07)},
{TEST, (max_x >> 2) & 0X80},
{ZMOW, (w)&0xFF},
{ZMOH, (h)&0xFF},
{ZMHH, ((h>>6)&0x04)|((w>>8)&0x03)},
{0, 0}
};
if (framesize <= FRAMESIZE_CIF) {
c.pclk_auto = 0;
c.pclk_div = 8;
c.clk_2x = 0;
c.clk_div = 0;
if(sensor->pixformat != PIXFORMAT_JPEG){
c.pclk_auto = 1;
c.clk_div = 7;
}
if (mode == OV2640_MODE_CIF) {
regs = ov2640_settings_to_cif;
} else if (framesize <= FRAMESIZE_SVGA) {
if(sensor->pixformat != PIXFORMAT_JPEG){
c.clk_div = 3;
}
} else if (mode == OV2640_MODE_SVGA) {
regs = ov2640_settings_to_svga;
} else {
regs = ov2640_settings_to_uxga;
c.pclk_div = 12;
}
WRITE_REG_OR_RETURN(BANK_DSP, R_BYPASS, R_BYPASS_DSP_BYPAS);
WRITE_REGS_OR_RETURN(regs);
if (sensor->pixformat == PIXFORMAT_JPEG && sensor->xclk_freq_hz == 10000000) {
if (framesize <= FRAMESIZE_CIF) {
WRITE_REG_OR_RETURN(BANK_SENSOR, CLKRC, CLKRC_2X_CIF);
} else if (framesize <= FRAMESIZE_SVGA) {
WRITE_REG_OR_RETURN(BANK_SENSOR, CLKRC, CLKRC_2X_SVGA);
} else {
WRITE_REG_OR_RETURN(BANK_SENSOR, CLKRC, CLKRC_2X_UXGA);
}
}
WRITE_REG_OR_RETURN(BANK_DSP, ZMOW, (w>>2)&0xFF); // OUTW[7:0] (real/4)
WRITE_REG_OR_RETURN(BANK_DSP, ZMOH, (h>>2)&0xFF); // OUTH[7:0] (real/4)
WRITE_REG_OR_RETURN(BANK_DSP, ZMHH, ((h>>8)&0x04)|((w>>10)&0x03)); // OUTH[8]/OUTW[9:8]
WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0x00);
WRITE_REGS_OR_RETURN(win_regs);
WRITE_REG_OR_RETURN(BANK_SENSOR, CLKRC, c.clk);
WRITE_REG_OR_RETURN(BANK_DSP, R_DVP_SP, c.pclk);
WRITE_REG_OR_RETURN(BANK_DSP, R_BYPASS, R_BYPASS_DSP_EN);
vTaskDelay(10 / portTICK_PERIOD_MS);
@@ -263,6 +193,43 @@ static int set_framesize(sensor_t *sensor, framesize_t framesize)
return ret;
}
static int set_framesize(sensor_t *sensor, framesize_t framesize)
{
int ret = 0;
uint16_t w = resolution[framesize].width;
uint16_t h = resolution[framesize].height;
aspect_ratio_t ratio = resolution[framesize].aspect_ratio;
uint16_t max_x = ratio_table[ratio].max_x;
uint16_t max_y = ratio_table[ratio].max_y;
uint16_t offset_x = ratio_table[ratio].offset_x;
uint16_t offset_y = ratio_table[ratio].offset_y;
ov2640_sensor_mode_t mode = OV2640_MODE_UXGA;
sensor->status.framesize = framesize;
if (framesize <= FRAMESIZE_CIF) {
mode = OV2640_MODE_CIF;
max_x /= 4;
max_y /= 4;
offset_x /= 4;
offset_y /= 4;
if(max_y > 296){
max_y = 296;
}
} else if (framesize <= FRAMESIZE_SVGA) {
mode = OV2640_MODE_SVGA;
max_x /= 2;
max_y /= 2;
offset_x /= 2;
offset_y /= 2;
}
ret = set_window(sensor, mode, offset_x, offset_y, max_x, max_y, w, h);
return ret;
}
static int set_contrast(sensor_t *sensor, int level)
{
int ret=0;
@@ -482,6 +449,46 @@ static int set_denoise(sensor_t *sensor, int level)
return -1;
}
static int get_reg(sensor_t *sensor, int reg, int mask)
{
int ret = read_reg(sensor, (reg >> 8) & 0x01, reg & 0xFF);
if(ret > 0){
ret &= mask;
}
return ret;
}
static int set_reg(sensor_t *sensor, int reg, int mask, int value)
{
int ret = 0;
ret = read_reg(sensor, (reg >> 8) & 0x01, reg & 0xFF);
if(ret < 0){
return ret;
}
value = (ret & ~mask) | (value & mask);
ret = write_reg(sensor, (reg >> 8) & 0x01, reg & 0xFF, value);
return ret;
}
static int set_res_raw(sensor_t *sensor, int startX, int startY, int endX, int endY, int offsetX, int offsetY, int totalX, int totalY, int outputX, int outputY, bool scale, bool binning)
{
return set_window(sensor, (ov2640_sensor_mode_t)startX, offsetX, offsetY, totalX, totalY, outputX, outputY);
}
static int _set_pll(sensor_t *sensor, int bypass, int multiplier, int sys_div, int root_2x, int pre_div, int seld5, int pclk_manual, int pclk_div)
{
return -1;
}
esp_err_t xclk_timer_conf(int ledc_timer, int xclk_freq_hz);
static int set_xclk(sensor_t *sensor, int timer, int xclk)
{
int ret = 0;
sensor->xclk_freq_hz = xclk * 1000000U;
ret = xclk_timer_conf(timer, sensor->xclk_freq_hz);
return ret;
}
static int init_status(sensor_t *sensor){
sensor->status.brightness = 0;
sensor->status.contrast = 0;
@@ -562,6 +569,12 @@ int ov2640_init(sensor_t *sensor)
//not supported
sensor->set_sharpness = set_sharpness;
sensor->set_denoise = set_denoise;
sensor->get_reg = get_reg;
sensor->set_reg = set_reg;
sensor->set_res_raw = set_res_raw;
sensor->set_pll = _set_pll;
sensor->set_xclk = set_xclk;
ESP_LOGD(TAG, "OV2640 Attached");
return 0;
}

158
sensors/ov3660.c
View File

@@ -124,7 +124,7 @@ static int write_addr_reg(uint8_t slv_addr, const uint16_t reg, uint16_t x_value
#define write_reg_bits(slv_addr, reg, mask, enable) set_reg_bits(slv_addr, reg, 0, mask, enable?mask:0)
int calc_sysclk(int xclk, bool pll_bypass, int pll_multiplier, int pll_sys_div, int pll_pre_div, bool pll_root_2x, int pll_seld5, bool pclk_manual, int pclk_div)
static int calc_sysclk(int xclk, bool pll_bypass, int pll_multiplier, int pll_sys_div, int pll_pre_div, bool pll_root_2x, int pll_seld5, bool pclk_manual, int pclk_div)
{
const int pll_pre_div2x_map[] = { 2, 3, 4, 6 };//values are multiplied by two to avoid floats
const int pll_seld52x_map[] = { 2, 2, 4, 5 };
@@ -252,12 +252,12 @@ static int set_image_options(sensor_t *sensor)
}
// binning
if (sensor->status.framesize > FRAMESIZE_SVGA) {
reg20 |= 0x40;
} else {
if (sensor->status.binning) {
reg20 |= 0x01;
reg21 |= 0x01;
reg4514_test |= 4;
} else {
reg20 |= 0x40;
}
// V-Flip
@@ -292,8 +292,18 @@ static int set_image_options(sensor_t *sensor)
ret = -1;
}
if (sensor->status.binning) {
ret = write_reg(sensor->slv_addr, 0x4520, 0x0b)
|| write_reg(sensor->slv_addr, X_INCREMENT, 0x31)//odd:3, even: 1
|| write_reg(sensor->slv_addr, Y_INCREMENT, 0x31);//odd:3, even: 1
} else {
ret = write_reg(sensor->slv_addr, 0x4520, 0xb0)
|| write_reg(sensor->slv_addr, X_INCREMENT, 0x11)//odd:1, even: 1
|| write_reg(sensor->slv_addr, Y_INCREMENT, 0x11);//odd:1, even: 1
}
ESP_LOGD(TAG, "Set Image Options: Compression: %u, Binning: %u, V-Flip: %u, H-Mirror: %u, Reg-4514: 0x%02x",
sensor->pixformat == PIXFORMAT_JPEG, sensor->status.framesize <= FRAMESIZE_SVGA, sensor->status.vflip, sensor->status.hmirror, reg4514);
sensor->pixformat == PIXFORMAT_JPEG, sensor->status.binning, sensor->status.vflip, sensor->status.hmirror, reg4514);
return ret;
}
@@ -303,51 +313,37 @@ static int set_framesize(sensor_t *sensor, framesize_t framesize)
framesize_t old_framesize = sensor->status.framesize;
sensor->status.framesize = framesize;
if(framesize >= FRAMESIZE_INVALID){
if(framesize > FRAMESIZE_QXGA){
ESP_LOGE(TAG, "Invalid framesize: %u", framesize);
return -1;
}
uint16_t w = resolution[framesize][0];
uint16_t h = resolution[framesize][1];
uint16_t w = resolution[framesize].width;
uint16_t h = resolution[framesize].height;
aspect_ratio_t ratio = resolution[sensor->status.framesize].aspect_ratio;
ratio_settings_t settings = ratio_table[ratio];
if (framesize > FRAMESIZE_SVGA) {
ret = write_reg(sensor->slv_addr, 0x4520, 0xb0)
|| write_reg(sensor->slv_addr, X_INCREMENT, 0x11)//odd:1, even: 1
|| write_reg(sensor->slv_addr, Y_INCREMENT, 0x11);//odd:1, even: 1
} else {
ret = write_reg(sensor->slv_addr, 0x4520, 0x0b)
|| write_reg(sensor->slv_addr, X_INCREMENT, 0x31)//odd:3, even: 1
|| write_reg(sensor->slv_addr, Y_INCREMENT, 0x31);//odd:3, even: 1
}
sensor->status.binning = (w <= (settings.max_width / 2) && h <= (settings.max_height / 2));
sensor->status.scale = !((w == settings.max_width && h == settings.max_height)
|| (w == (settings.max_width / 2) && h == (settings.max_height / 2)));
if (ret) {
goto fail;
}
ret = write_addr_reg(sensor->slv_addr, X_ADDR_ST_H, 0, 0)
|| write_addr_reg(sensor->slv_addr, X_ADDR_END_H, 2079, 1547)
ret = write_addr_reg(sensor->slv_addr, X_ADDR_ST_H, settings.start_x, settings.start_y)
|| write_addr_reg(sensor->slv_addr, X_ADDR_END_H, settings.end_x, settings.end_y)
|| write_addr_reg(sensor->slv_addr, X_OUTPUT_SIZE_H, w, h);
if (ret) {
goto fail;
}
if (framesize > FRAMESIZE_SVGA) {
ret = write_addr_reg(sensor->slv_addr, X_TOTAL_SIZE_H, 2300, 1564)
|| write_addr_reg(sensor->slv_addr, X_OFFSET_H, 16, 6);
if (sensor->status.binning) {
ret = write_addr_reg(sensor->slv_addr, X_TOTAL_SIZE_H, settings.total_x, (settings.total_y / 2) + 1)
|| write_addr_reg(sensor->slv_addr, X_OFFSET_H, 8, 2);
} else {
if (framesize == FRAMESIZE_SVGA) {
ret = write_addr_reg(sensor->slv_addr, X_TOTAL_SIZE_H, 2300, 788);
} else {
ret = write_addr_reg(sensor->slv_addr, X_TOTAL_SIZE_H, 2050, 788);
}
if (ret == 0) {
ret = write_addr_reg(sensor->slv_addr, X_OFFSET_H, 8, 2);
}
ret = write_addr_reg(sensor->slv_addr, X_TOTAL_SIZE_H, settings.total_x, settings.total_y)
|| write_addr_reg(sensor->slv_addr, X_OFFSET_H, 16, 6);
}
if (ret == 0) {
ret = write_reg_bits(sensor->slv_addr, ISP_CONTROL_01, 0x20, framesize != FRAMESIZE_QXGA);
ret = write_reg_bits(sensor->slv_addr, ISP_CONTROL_01, 0x20, sensor->status.scale);
}
if (ret == 0) {
@@ -880,6 +876,92 @@ static int set_denoise(sensor_t *sensor, int level)
return ret;
}
static int get_reg(sensor_t *sensor, int reg, int mask)
{
int ret = 0, ret2 = 0;
if(mask > 0xFF){
ret = read_reg16(sensor->slv_addr, reg);
if(ret >= 0 && mask > 0xFFFF){
ret2 = read_reg(sensor->slv_addr, reg+2);
if(ret2 >= 0){
ret = (ret << 8) | ret2 ;
} else {
ret = ret2;
}
}
} else {
ret = read_reg(sensor->slv_addr, reg);
}
if(ret > 0){
ret &= mask;
}
return ret;
}
static int set_reg(sensor_t *sensor, int reg, int mask, int value)
{
int ret = 0, ret2 = 0;
if(mask > 0xFF){
ret = read_reg16(sensor->slv_addr, reg);
if(ret >= 0 && mask > 0xFFFF){
ret2 = read_reg(sensor->slv_addr, reg+2);
if(ret2 >= 0){
ret = (ret << 8) | ret2 ;
} else {
ret = ret2;
}
}
} else {
ret = read_reg(sensor->slv_addr, reg);
}
if(ret < 0){
return ret;
}
value = (ret & ~mask) | (value & mask);
if(mask > 0xFFFF){
ret = write_reg16(sensor->slv_addr, reg, value >> 8);
if(ret >= 0){
ret = write_reg(sensor->slv_addr, reg+2, value & 0xFF);
}
} else if(mask > 0xFF){
ret = write_reg16(sensor->slv_addr, reg, value);
} else {
ret = write_reg(sensor->slv_addr, reg, value);
}
return ret;
}
static int set_res_raw(sensor_t *sensor, int startX, int startY, int endX, int endY, int offsetX, int offsetY, int totalX, int totalY, int outputX, int outputY, bool scale, bool binning)
{
int ret = 0;
ret = write_addr_reg(sensor->slv_addr, X_ADDR_ST_H, startX, startY)
|| write_addr_reg(sensor->slv_addr, X_ADDR_END_H, endX, endY)
|| write_addr_reg(sensor->slv_addr, X_OFFSET_H, offsetX, offsetY)
|| write_addr_reg(sensor->slv_addr, X_TOTAL_SIZE_H, totalX, totalY)
|| write_addr_reg(sensor->slv_addr, X_OUTPUT_SIZE_H, outputX, outputY)
|| write_reg_bits(sensor->slv_addr, ISP_CONTROL_01, 0x20, scale);
if(!ret){
sensor->status.scale = scale;
sensor->status.binning = binning;
ret = set_image_options(sensor);
}
return ret;
}
static int _set_pll(sensor_t *sensor, int bypass, int multiplier, int sys_div, int root_2x, int pre_div, int seld5, int pclk_manual, int pclk_div)
{
return set_pll(sensor, bypass > 0, multiplier, sys_div, pre_div, root_2x > 0, seld5, pclk_manual > 0, pclk_div);
}
esp_err_t xclk_timer_conf(int ledc_timer, int xclk_freq_hz);
static int set_xclk(sensor_t *sensor, int timer, int xclk)
{
int ret = 0;
sensor->xclk_freq_hz = xclk * 1000000U;
ret = xclk_timer_conf(timer, sensor->xclk_freq_hz);
return ret;
}
static int init_status(sensor_t *sensor)
{
sensor->status.brightness = 0;
@@ -941,5 +1023,11 @@ int ov3660_init(sensor_t *sensor)
sensor->set_raw_gma = set_raw_gma_dsp;
sensor->set_lenc = set_lenc_dsp;
sensor->set_denoise = set_denoise;
sensor->get_reg = get_reg;
sensor->set_reg = set_reg;
sensor->set_res_raw = set_res_raw;
sensor->set_pll = _set_pll;
sensor->set_xclk = set_xclk;
return 0;
}

1105
sensors/ov5640.c Executable file
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File diff suppressed because it is too large Load Diff

4
sensors/ov7725.c
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@@ -176,8 +176,8 @@ static int set_pixformat(sensor_t *sensor, pixformat_t pixformat)
static int set_framesize(sensor_t *sensor, framesize_t framesize)
{
int ret=0;
uint16_t w = resolution[framesize][0];
uint16_t h = resolution[framesize][1];
uint16_t w = resolution[framesize].width;
uint16_t h = resolution[framesize].height;
uint8_t reg = SCCB_Read(sensor->slv_addr, COM7);
sensor->status.framesize = framesize;

55
sensors/private_include/ov2640_settings.h
View File

@@ -19,6 +19,48 @@
#include "esp_attr.h"
#include "ov2640_regs.h"
typedef enum {
OV2640_MODE_UXGA, OV2640_MODE_SVGA, OV2640_MODE_CIF, OV2640_MODE_MAX
} ov2640_sensor_mode_t;
typedef struct {
union {
struct {
uint8_t pclk_div:7;
uint8_t pclk_auto:1;
};
uint8_t pclk;
};
union {
struct {
uint8_t clk_div:6;
uint8_t reserved:1;
uint8_t clk_2x:1;
};
uint8_t clk;
};
} ov2640_clk_t;
typedef struct {
uint16_t offset_x;
uint16_t offset_y;
uint16_t max_x;
uint16_t max_y;
} ov2640_ratio_settings_t;
static const DRAM_ATTR ov2640_ratio_settings_t ratio_table[] = {
// ox, oy, mx, my
{ 0, 0, 1600, 1200 }, //4x3
{ 8, 72, 1584, 1056 }, //3x2
{ 0, 100, 1600, 1000 }, //16x10
{ 0, 120, 1600, 960 }, //5x3
{ 0, 150, 1600, 900 }, //16x9
{ 2, 258, 1596, 684 }, //21x9
{ 50, 0, 1500, 1200 }, //5x4
{ 200, 0, 1200, 1200 }, //1x1
{ 462, 0, 676, 1200 } //9x16
};
// 30fps@24MHz
const DRAM_ATTR uint8_t ov2640_settings_cif[][2] = {
{BANK_SEL, BANK_DSP},
@@ -193,7 +235,7 @@ const DRAM_ATTR uint8_t ov2640_settings_to_cif[][2] = {
{VSTART, 0x00},
{VSTOP, 0x25},
{CLKRC, 0x01},
//{CLKRC, 0x00},
{BD50, 0xca},
{BD60, 0xa8},
{0x5a, 0x23},
@@ -228,7 +270,7 @@ const DRAM_ATTR uint8_t ov2640_settings_to_cif[][2] = {
{CTRL2, CTRL2_DCW_EN | 0x1D},
{CTRLI, CTRLI_LP_DP | 0x00},
{R_DVP_SP, 0x82},
//{R_DVP_SP, 0x08},
{0, 0}
};
@@ -244,7 +286,7 @@ const DRAM_ATTR uint8_t ov2640_settings_to_svga[][2] = {
{VSTART, 0x00},
{VSTOP, 0x4b},
{CLKRC, 0x01},
//{CLKRC, 0x00},
{0x37, 0xc0},
{BD50, 0xca},
{BD60, 0xa8},
@@ -281,7 +323,7 @@ const DRAM_ATTR uint8_t ov2640_settings_to_svga[][2] = {
{CTRL2, CTRL2_DCW_EN | 0x1D},
{CTRLI, CTRLI_LP_DP | 0x00},
{R_DVP_SP, 0x80},
//{R_DVP_SP, 0x08},
{0, 0}
};
@@ -297,7 +339,7 @@ const DRAM_ATTR uint8_t ov2640_settings_to_uxga[][2] = {
{VSTART, 0x01},
{VSTOP, 0x97},
{CLKRC, 0x01},
//{CLKRC, 0x00},
{0x3d, 0x34},
{BD50, 0xbb},
{BD60, 0x9c},
@@ -333,7 +375,7 @@ const DRAM_ATTR uint8_t ov2640_settings_to_uxga[][2] = {
{CTRL2, CTRL2_DCW_EN | 0x1d},
{CTRLI, 0x00},
{R_DVP_SP, 0x82},
//{R_DVP_SP, 0x06},
{0, 0}
};
@@ -348,7 +390,6 @@ const DRAM_ATTR uint8_t ov2640_settings_jpeg3[][2] = {
{0xDF, 0x80},
{0x33, 0x80},
{0x3C, 0x10},
{R_DVP_SP, 0x04},
{0xEB, 0x30},
{0xDD, 0x7F},
{RESET, 0x00},

62
sensors/private_include/ov3660_settings.h
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@@ -6,10 +6,23 @@
#include "esp_attr.h"
#include "ov3660_regs.h"
static const ratio_settings_t ratio_table[] = {
// mw, mh, sx, sy, ex, ey, ox, oy, tx, ty
{ 2048, 1536, 0, 0, 2079, 1547, 16, 6, 2300, 1564 }, //4x3
{ 1920, 1280, 64, 128, 2015, 1419, 16, 6, 2172, 1436 }, //3x2
{ 2048, 1280, 0, 128, 2079, 1419, 16, 6, 2300, 1436 }, //16x10
{ 1920, 1152, 64, 192, 2015, 1355, 16, 6, 2172, 1372 }, //5x3
{ 1920, 1080, 64, 242, 2015, 1333, 16, 6, 2172, 1322 }, //16x9
{ 2048, 880, 0, 328, 2079, 1219, 16, 6, 2300, 1236 }, //21x9
{ 1920, 1536, 64, 0, 2015, 1547, 16, 6, 2172, 1564 }, //5x4
{ 1536, 1536, 256, 0, 1823, 1547, 16, 6, 2044, 1564 }, //1x1
{ 864, 1536, 592, 0, 1487, 1547, 16, 6, 2044, 1564 } //9x16
};
#define REG_DLY 0xffff
#define REGLIST_TAIL 0x0000
const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
static const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
{SYSTEM_CTROL0, 0x82}, // software reset
{REG_DLY, 10}, // delay 10ms
@@ -131,22 +144,23 @@ const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
{0x538a, 0x01},
{0x538b, 0x98},
{0x5481, 0x05},
{0x5482, 0x09},
{0x5483, 0x10},
{0x5484, 0x3a},
{0x5485, 0x4c},
{0x5486, 0x5a},
{0x5487, 0x68},
{0x5488, 0x74},
{0x5489, 0x80},
{0x548a, 0x8e},
{0x548b, 0xa4},
{0x548c, 0xb4},
{0x548d, 0xc8},
{0x548e, 0xde},
{0x548f, 0xf0},
{0x5490, 0x15},
{0x5480, 0x01},
// {0x5481, 0x05},
// {0x5482, 0x09},
// {0x5483, 0x10},
// {0x5484, 0x3a},
// {0x5485, 0x4c},
// {0x5486, 0x5a},
// {0x5487, 0x68},
// {0x5488, 0x74},
// {0x5489, 0x80},
// {0x548a, 0x8e},
// {0x548b, 0xa4},
// {0x548c, 0xb4},
// {0x548d, 0xc8},
// {0x548e, 0xde},
// {0x548f, 0xf0},
// {0x5490, 0x15},
{0x5000, 0xa7},
{0x5800, 0x0C},
@@ -247,7 +261,7 @@ const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
{REGLIST_TAIL, 0x00}, // tail
};
const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = {
static const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{0x3002, 0x00},//0x1c to 0x00 !!!
@@ -256,30 +270,30 @@ const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = {
{REGLIST_TAIL, 0x00}, // tail
};
const DRAM_ATTR uint16_t sensor_fmt_raw[][2] = {
static const DRAM_ATTR uint16_t sensor_fmt_raw[][2] = {
{FORMAT_CTRL00, 0x00}, // RAW
{REGLIST_TAIL, 0x00}
};
const DRAM_ATTR uint16_t sensor_fmt_grayscale[][2] = {
static const DRAM_ATTR uint16_t sensor_fmt_grayscale[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x10}, // Y8
{REGLIST_TAIL, 0x00}
};
const DRAM_ATTR uint16_t sensor_fmt_yuv422[][2] = {
static const DRAM_ATTR uint16_t sensor_fmt_yuv422[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{REGLIST_TAIL, 0x00}
};
const DRAM_ATTR uint16_t sensor_fmt_rgb565[][2] = {
static const DRAM_ATTR uint16_t sensor_fmt_rgb565[][2] = {
{FORMAT_CTRL, 0x01}, // RGB
{FORMAT_CTRL00, 0x61}, // RGB565 (BGR)
{REGLIST_TAIL, 0x00}
};
const DRAM_ATTR uint8_t sensor_saturation_levels[9][11] = {
static const DRAM_ATTR uint8_t sensor_saturation_levels[9][11] = {
{0x1d, 0x60, 0x03, 0x07, 0x48, 0x4f, 0x4b, 0x40, 0x0b, 0x01, 0x98},//-4
{0x1d, 0x60, 0x03, 0x08, 0x54, 0x5c, 0x58, 0x4b, 0x0d, 0x01, 0x98},//-3
{0x1d, 0x60, 0x03, 0x0a, 0x60, 0x6a, 0x64, 0x56, 0x0e, 0x01, 0x98},//-2
@@ -291,7 +305,7 @@ const DRAM_ATTR uint8_t sensor_saturation_levels[9][11] = {
{0x1d, 0x60, 0x03, 0x11, 0xa8, 0xb9, 0xaf, 0x96, 0x19, 0x01, 0x98},//+4
};
const DRAM_ATTR uint8_t sensor_special_effects[7][4] = {
static const DRAM_ATTR uint8_t sensor_special_effects[7][4] = {
{0x06, 0x40, 0x2c, 0x08},//Normal
{0x46, 0x40, 0x28, 0x08},//Negative
{0x1e, 0x80, 0x80, 0x08},//Grayscale

9
sensors/private_include/ov5640.h Executable file
View File

@@ -0,0 +1,9 @@
#ifndef __OV5640_H__
#define __OV5640_H__
#include "sensor.h"
int ov5640_init(sensor_t *sensor);
#endif // __OV5640_H__

213
sensors/private_include/ov5640_regs.h Executable file
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@@ -0,0 +1,213 @@
/*
* OV5640 register definitions.
*/
#ifndef __OV5640_REG_REGS_H__
#define __OV5640_REG_REGS_H__
/* system control registers */
#define SYSTEM_CTROL0 0x3008 // Bit[7]: Software reset
// Bit[6]: Software power down
// Bit[5]: Reserved
// Bit[4]: SRB clock SYNC enable
// Bit[3]: Isolation suspend select
// Bit[2:0]: Not used
#define DRIVE_CAPABILITY 0x302c // Bit[7:6]:
// 00: 1x
// 01: 2x
// 10: 3x
// 11: 4x
#define SC_PLLS_CTRL0 0x303a // Bit[7]: PLLS bypass
#define SC_PLLS_CTRL1 0x303b // Bit[4:0]: PLLS multiplier
#define SC_PLLS_CTRL2 0x303c // Bit[6:4]: PLLS charge pump control
// Bit[3:0]: PLLS system divider
#define SC_PLLS_CTRL3 0x303d // Bit[5:4]: PLLS pre-divider
// 00: 1
// 01: 1.5
// 10: 2
// 11: 3
// Bit[2]: PLLS root-divider - 1
// Bit[1:0]: PLLS seld5
// 00: 1
// 01: 1
// 10: 2
// 11: 2.5
/* AEC/AGC control functions */
#define AEC_PK_MANUAL 0x3503 // AEC Manual Mode Control
// Bit[7:6]: Reserved
// Bit[5]: Gain delay option
// Valid when 0x3503[4]=1’b0
// 0: Delay one frame latch
// 1: One frame latch
// Bit[4:2]: Reserved
// Bit[1]: AGC manual
// 0: Auto enable
// 1: Manual enable
// Bit[0]: AEC manual
// 0: Auto enable
// 1: Manual enable
//gain = {0x350A[1:0], 0x350B[7:0]} / 16
#define X_ADDR_ST_H 0x3800 //Bit[3:0]: X address start[11:8]
#define X_ADDR_ST_L 0x3801 //Bit[7:0]: X address start[7:0]
#define Y_ADDR_ST_H 0x3802 //Bit[2:0]: Y address start[10:8]
#define Y_ADDR_ST_L 0x3803 //Bit[7:0]: Y address start[7:0]
#define X_ADDR_END_H 0x3804 //Bit[3:0]: X address end[11:8]
#define X_ADDR_END_L 0x3805 //Bit[7:0]:
#define Y_ADDR_END_H 0x3806 //Bit[2:0]: Y address end[10:8]
#define Y_ADDR_END_L 0x3807 //Bit[7:0]:
// Size after scaling
#define X_OUTPUT_SIZE_H 0x3808 //Bit[3:0]: DVP output horizontal width[11:8]
#define X_OUTPUT_SIZE_L 0x3809 //Bit[7:0]:
#define Y_OUTPUT_SIZE_H 0x380a //Bit[2:0]: DVP output vertical height[10:8]
#define Y_OUTPUT_SIZE_L 0x380b //Bit[7:0]:
#define X_TOTAL_SIZE_H 0x380c //Bit[3:0]: Total horizontal size[11:8]
#define X_TOTAL_SIZE_L 0x380d //Bit[7:0]:
#define Y_TOTAL_SIZE_H 0x380e //Bit[7:0]: Total vertical size[15:8]
#define Y_TOTAL_SIZE_L 0x380f //Bit[7:0]:
#define X_OFFSET_H 0x3810 //Bit[3:0]: ISP horizontal offset[11:8]
#define X_OFFSET_L 0x3811 //Bit[7:0]:
#define Y_OFFSET_H 0x3812 //Bit[2:0]: ISP vertical offset[10:8]
#define Y_OFFSET_L 0x3813 //Bit[7:0]:
#define X_INCREMENT 0x3814 //Bit[7:4]: Horizontal odd subsample increment
//Bit[3:0]: Horizontal even subsample increment
#define Y_INCREMENT 0x3815 //Bit[7:4]: Vertical odd subsample increment
//Bit[3:0]: Vertical even subsample increment
// Size before scaling
//#define X_INPUT_SIZE (X_ADDR_END - X_ADDR_ST + 1 - (2 * X_OFFSET))
//#define Y_INPUT_SIZE (Y_ADDR_END - Y_ADDR_ST + 1 - (2 * Y_OFFSET))
/* mirror and flip registers */
#define TIMING_TC_REG20 0x3820 // Timing Control Register
// Bit[2:1]: Vertical flip enable
// 00: Normal
// 11: Vertical flip
// Bit[0]: Vertical binning enable
#define TIMING_TC_REG21 0x3821 // Timing Control Register
// Bit[5]: Compression Enable
// Bit[2:1]: Horizontal mirror enable
// 00: Normal
// 11: Horizontal mirror
// Bit[0]: Horizontal binning enable
#define PCLK_RATIO 0x3824 // Bit[4:0]: PCLK ratio manual
/* frame control registers */
#define FRAME_CTRL01 0x4201 // Control Passed Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// Bit[3:0]: Frame ON number
#define FRAME_CTRL02 0x4202 // Control Masked Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// BIT[3:0]: Frame OFF number
/* format control registers */
#define FORMAT_CTRL00 0x4300
#define CLOCK_POL_CONTROL 0x4740// Bit[5]: PCLK polarity 0: active low
// 1: active high
// Bit[3]: Gate PCLK under VSYNC
// Bit[2]: Gate PCLK under HREF
// Bit[1]: HREF polarity
// 0: active low
// 1: active high
// Bit[0] VSYNC polarity
// 0: active low
// 1: active high
#define ISP_CONTROL_01 0x5001 // Bit[5]: Scale enable
// 0: Disable
// 1: Enable
/* output format control registers */
#define FORMAT_CTRL 0x501F // Format select
// Bit[2:0]:
// 000: YUV422
// 001: RGB
// 010: Dither
// 011: RAW after DPC
// 101: RAW after CIP
/* ISP top control registers */
#define PRE_ISP_TEST_SETTING_1 0x503D // Bit[7]: Test enable
// 0: Test disable
// 1: Color bar enable
// Bit[6]: Rolling
// Bit[5]: Transparent
// Bit[4]: Square black and white
// Bit[3:2]: Color bar style
// 00: Standard 8 color bar
// 01: Gradual change at vertical mode 1
// 10: Gradual change at horizontal
// 11: Gradual change at vertical mode 2
// Bit[1:0]: Test select
// 00: Color bar
// 01: Random data
// 10: Square data
// 11: Black image
//exposure = {0x3500[3:0], 0x3501[7:0], 0x3502[7:0]} / 16 × tROW
#define SCALE_CTRL_1 0x5601 // Bit[6:4]: HDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
// Bit[2:0]: VDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
#define SCALE_CTRL_2 0x5602 // X_SCALE High Bits
#define SCALE_CTRL_3 0x5603 // X_SCALE Low Bits
#define SCALE_CTRL_4 0x5604 // Y_SCALE High Bits
#define SCALE_CTRL_5 0x5605 // Y_SCALE Low Bits
#define SCALE_CTRL_6 0x5606 // Bit[3:0]: V Offset
#define VFIFO_CTRL0C 0x460C // Bit[1]: PCLK manual enable
// 0: Auto
// 1: Manual by PCLK_RATIO
#define VFIFO_X_SIZE_H 0x4602
#define VFIFO_X_SIZE_L 0x4603
#define VFIFO_Y_SIZE_H 0x4604
#define VFIFO_Y_SIZE_L 0x4605
#define COMPRESSION_CTRL00 0x4400 //
#define COMPRESSION_CTRL01 0x4401 //
#define COMPRESSION_CTRL02 0x4402 //
#define COMPRESSION_CTRL03 0x4403 //
#define COMPRESSION_CTRL04 0x4404 //
#define COMPRESSION_CTRL05 0x4405 //
#define COMPRESSION_CTRL06 0x4406 //
#define COMPRESSION_CTRL07 0x4407 // Bit[5:0]: QS
#define COMPRESSION_ISI_CTRL 0x4408 //
#define COMPRESSION_CTRL09 0x4409 //
#define COMPRESSION_CTRL0a 0x440a //
#define COMPRESSION_CTRL0b 0x440b //
#define COMPRESSION_CTRL0c 0x440c //
#define COMPRESSION_CTRL0d 0x440d //
#define COMPRESSION_CTRL0E 0x440e //
/**
* @brief register value
*/
#define TEST_COLOR_BAR 0xC0 /* Enable Color Bar roling Test */
#define AEC_PK_MANUAL_AGC_MANUALEN 0x02 /* Enable AGC Manual enable */
#define AEC_PK_MANUAL_AEC_MANUALEN 0x01 /* Enable AEC Manual enable */
#define TIMING_TC_REG20_VFLIP 0x06 /* Vertical flip enable */
#define TIMING_TC_REG21_HMIRROR 0x06 /* Horizontal mirror enable */
#endif // __OV3660_REG_REGS_H__

334
sensors/private_include/ov5640_settings.h Normal file
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@@ -0,0 +1,334 @@
#ifndef _OV5640_SETTINGS_H_
#define _OV5640_SETTINGS_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "ov5640_regs.h"
static const ratio_settings_t ratio_table[] = {
// mw, mh, sx, sy, ex, ey, ox, oy, tx, ty
{ 2560, 1920, 0, 0, 2623, 1951, 32, 16, 2844, 1968 }, //4x3
{ 2560, 1704, 0, 110, 2623, 1843, 32, 16, 2844, 1752 }, //3x2
{ 2560, 1600, 0, 160, 2623, 1791, 32, 16, 2844, 1648 }, //16x10
{ 2560, 1536, 0, 192, 2623, 1759, 32, 16, 2844, 1584 }, //5x3
{ 2560, 1440, 0, 240, 2623, 1711, 32, 16, 2844, 1488 }, //16x9
{ 2560, 1080, 0, 420, 2623, 1531, 32, 16, 2844, 1128 }, //21x9
{ 2400, 1920, 80, 0, 2543, 1951, 32, 16, 2684, 1968 }, //5x4
{ 1920, 1920, 320, 0, 2543, 1951, 32, 16, 2684, 1968 }, //1x1
{ 1088, 1920, 736, 0, 1887, 1951, 32, 16, 1884, 1968 } //9x16
};
#define REG_DLY 0xffff
#define REGLIST_TAIL 0x0000
static const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
{SYSTEM_CTROL0, 0x82}, // software reset
{REG_DLY, 10}, // delay 10ms
{SYSTEM_CTROL0, 0x42}, // power down
//enable pll
{0x3103, 0x13},
//io direction
{0x3017, 0xff},
{0x3018, 0xff},
{DRIVE_CAPABILITY, 0xc3},
{CLOCK_POL_CONTROL, 0x21},
{0x4713, 0x02},//jpg mode select
{ISP_CONTROL_01, 0x83}, // turn color matrix, awb and SDE
//sys reset
{0x3000, 0x00},
{0x3002, 0x1c},
//clock enable
{0x3004, 0xff},
{0x3006, 0xc3},
//isp control
{0x5000, 0xa7},
{ISP_CONTROL_01, 0xa3},//+scaling?
{0x5003, 0x08},//special_effect
//unknown
{0x370c, 0x02},//!!IMPORTANT
{0x3634, 0x40},//!!IMPORTANT
//AEC/AGC
{0x3a02, 0x03},
{0x3a03, 0xd8},
{0x3a08, 0x01},
{0x3a09, 0x27},
{0x3a0a, 0x00},
{0x3a0b, 0xf6},
{0x3a0d, 0x04},
{0x3a0e, 0x03},
{0x3a0f, 0x30},//ae_level
{0x3a10, 0x28},//ae_level
{0x3a11, 0x60},//ae_level
{0x3a13, 0x43},
{0x3a14, 0x03},
{0x3a15, 0xd8},
{0x3a18, 0x00},//gainceiling
{0x3a19, 0xf8},//gainceiling
{0x3a1b, 0x30},//ae_level
{0x3a1e, 0x26},//ae_level
{0x3a1f, 0x14},//ae_level
//vcm debug
{0x3600, 0x08},
{0x3601, 0x33},
//50/60Hz
{0x3c01, 0xa4},
{0x3c04, 0x28},
{0x3c05, 0x98},
{0x3c06, 0x00},
{0x3c07, 0x08},
{0x3c08, 0x00},
{0x3c09, 0x1c},
{0x3c0a, 0x9c},
{0x3c0b, 0x40},
{0x460c, 0x22},//disable jpeg footer
//BLC
{0x4001, 0x02},
{0x4004, 0x02},
//AWB
{0x5180, 0xff},
{0x5181, 0xf2},
{0x5182, 0x00},
{0x5183, 0x14},
{0x5184, 0x25},
{0x5185, 0x24},
{0x5186, 0x09},
{0x5187, 0x09},
{0x5188, 0x09},
{0x5189, 0x75},
{0x518a, 0x54},
{0x518b, 0xe0},
{0x518c, 0xb2},
{0x518d, 0x42},
{0x518e, 0x3d},
{0x518f, 0x56},
{0x5190, 0x46},
{0x5191, 0xf8},
{0x5192, 0x04},
{0x5193, 0x70},
{0x5194, 0xf0},
{0x5195, 0xf0},
{0x5196, 0x03},
{0x5197, 0x01},
{0x5198, 0x04},
{0x5199, 0x12},
{0x519a, 0x04},
{0x519b, 0x00},
{0x519c, 0x06},
{0x519d, 0x82},
{0x519e, 0x38},
//color matrix (Saturation)
{0x5381, 0x1e},
{0x5382, 0x5b},
{0x5383, 0x08},
{0x5384, 0x0a},
{0x5385, 0x7e},
{0x5386, 0x88},
{0x5387, 0x7c},
{0x5388, 0x6c},
{0x5389, 0x10},
{0x538a, 0x01},
{0x538b, 0x98},
//CIP control (Sharpness)
{0x5300, 0x10},//sharpness
{0x5301, 0x10},//sharpness
{0x5302, 0x18},//sharpness
{0x5303, 0x19},//sharpness
{0x5304, 0x10},
{0x5305, 0x10},
{0x5306, 0x08},//denoise
{0x5307, 0x16},
{0x5308, 0x40},
{0x5309, 0x10},//sharpness
{0x530a, 0x10},//sharpness
{0x530b, 0x04},//sharpness
{0x530c, 0x06},//sharpness
//GAMMA
{0x5480, 0x01},
{0x5481, 0x00},
{0x5482, 0x1e},
{0x5483, 0x3b},
{0x5484, 0x58},
{0x5485, 0x66},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x83},
{0x5489, 0x8f},
{0x548a, 0x98},
{0x548b, 0xa6},
{0x548c, 0xb8},
{0x548d, 0xca},
{0x548e, 0xd7},
{0x548f, 0xe3},
{0x5490, 0x1d},
//Special Digital Effects (SDE) (UV adjust)
{0x5580, 0x06},//enable brightness and contrast
{0x5583, 0x40},//special_effect
{0x5584, 0x10},//special_effect
{0x5586, 0x20},//contrast
{0x5587, 0x00},//brightness
{0x5588, 0x00},//brightness
{0x5589, 0x10},
{0x558a, 0x00},
{0x558b, 0xf8},
{0x501d, 0x40},// enable manual offset of contrast
//power on
{0x3008, 0x02},
//50Hz
{0x3c00, 0x04},
{REG_DLY, 300},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{0x3002, 0x00},//0x1c to 0x00 !!!
{0x3006, 0xff},//0xc3 to 0xff !!!
{0x471c, 0x50},//0xd0 to 0x50 !!!
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_raw[][2] = {
{FORMAT_CTRL, 0x03}, // RAW (DPC)
{FORMAT_CTRL00, 0x00}, // RAW
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_grayscale[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x10}, // Y8
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_yuv422[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_rgb565[][2] = {
{FORMAT_CTRL, 0x01}, // RGB
{FORMAT_CTRL00, 0x61}, // RGB565 (BGR)
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint8_t sensor_saturation_levels[9][11] = {
{0x1d, 0x60, 0x03, 0x07, 0x48, 0x4f, 0x4b, 0x40, 0x0b, 0x01, 0x98},//-4
{0x1d, 0x60, 0x03, 0x08, 0x54, 0x5c, 0x58, 0x4b, 0x0d, 0x01, 0x98},//-3
{0x1d, 0x60, 0x03, 0x0a, 0x60, 0x6a, 0x64, 0x56, 0x0e, 0x01, 0x98},//-2
{0x1d, 0x60, 0x03, 0x0b, 0x6c, 0x77, 0x70, 0x60, 0x10, 0x01, 0x98},//-1
{0x1d, 0x60, 0x03, 0x0c, 0x78, 0x84, 0x7d, 0x6b, 0x12, 0x01, 0x98},//0
{0x1d, 0x60, 0x03, 0x0d, 0x84, 0x91, 0x8a, 0x76, 0x14, 0x01, 0x98},//+1
{0x1d, 0x60, 0x03, 0x0e, 0x90, 0x9e, 0x96, 0x80, 0x16, 0x01, 0x98},//+2
{0x1d, 0x60, 0x03, 0x10, 0x9c, 0xac, 0xa2, 0x8b, 0x17, 0x01, 0x98},//+3
{0x1d, 0x60, 0x03, 0x11, 0xa8, 0xb9, 0xaf, 0x96, 0x19, 0x01, 0x98},//+4
};
static const DRAM_ATTR uint8_t sensor_special_effects[7][4] = {
{0x06, 0x40, 0x2c, 0x08},//Normal
{0x46, 0x40, 0x28, 0x08},//Negative
{0x1e, 0x80, 0x80, 0x08},//Grayscale
{0x1e, 0x80, 0xc0, 0x08},//Red Tint
{0x1e, 0x60, 0x60, 0x08},//Green Tint
{0x1e, 0xa0, 0x40, 0x08},//Blue Tint
{0x1e, 0x40, 0xa0, 0x08},//Sepia
};
static const DRAM_ATTR uint16_t sensor_regs_gamma0[][2] = {
{0x5480, 0x01},
{0x5481, 0x08},
{0x5482, 0x14},
{0x5483, 0x28},
{0x5484, 0x51},
{0x5485, 0x65},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x87},
{0x5489, 0x91},
{0x548a, 0x9a},
{0x548b, 0xaa},
{0x548c, 0xb8},
{0x548d, 0xcd},
{0x548e, 0xdd},
{0x548f, 0xea},
{0x5490, 0x1d}
};
static const DRAM_ATTR uint16_t sensor_regs_gamma1[][2] = {
{0x5480, 0x1},
{0x5481, 0x0},
{0x5482, 0x1e},
{0x5483, 0x3b},
{0x5484, 0x58},
{0x5485, 0x66},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x83},
{0x5489, 0x8f},
{0x548a, 0x98},
{0x548b, 0xa6},
{0x548c, 0xb8},
{0x548d, 0xca},
{0x548e, 0xd7},
{0x548f, 0xe3},
{0x5490, 0x1d}
};
static const DRAM_ATTR uint16_t sensor_regs_awb0[][2] = {
{0x5180, 0xff},
{0x5181, 0xf2},
{0x5182, 0x00},
{0x5183, 0x14},
{0x5184, 0x25},
{0x5185, 0x24},
{0x5186, 0x09},
{0x5187, 0x09},
{0x5188, 0x09},
{0x5189, 0x75},
{0x518a, 0x54},
{0x518b, 0xe0},
{0x518c, 0xb2},
{0x518d, 0x42},
{0x518e, 0x3d},
{0x518f, 0x56},
{0x5190, 0x46},
{0x5191, 0xf8},
{0x5192, 0x04},
{0x5193, 0x70},
{0x5194, 0xf0},
{0x5195, 0xf0},
{0x5196, 0x03},
{0x5197, 0x01},
{0x5198, 0x04},
{0x5199, 0x12},
{0x519a, 0x04},
{0x519b, 0x00},
{0x519c, 0x06},
{0x519d, 0x82},
{0x519e, 0x38}
};
#endif