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me-no-dev
2018-11-15 14:22:09 +01:00
commit 0d2547a501
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479
sensors/ov2640.c Executable file
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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV2640 driver.
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "sccb.h"
#include "ov2640.h"
#include "ov2640_regs.h"
#include "ov2640_settings.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#if defined(ARDUINO_ARCH_ESP32) && defined(CONFIG_ARDUHAL_ESP_LOG)
#include "esp32-hal-log.h"
#else
#include "esp_log.h"
static const char* TAG = "ov2640";
#endif
static volatile ov2640_bank_t reg_bank = BANK_MAX;
static int set_bank(sensor_t *sensor, ov2640_bank_t bank)
{
int res = 0;
if (bank != reg_bank) {
reg_bank = bank;
res = SCCB_Write(sensor->slv_addr, BANK_SEL, bank);
}
return res;
}
static int write_regs(sensor_t *sensor, const uint8_t (*regs)[2])
{
int i=0, res = 0;
while (regs[i][0]) {
if (regs[i][0] == BANK_SEL) {
res = set_bank(sensor, regs[i][1]);
} else {
res = SCCB_Write(sensor->slv_addr, regs[i][0], regs[i][1]);
}
if (res) {
return res;
}
i++;
}
return res;
}
static int write_reg(sensor_t *sensor, ov2640_bank_t bank, uint8_t reg, uint8_t value)
{
int ret = set_bank(sensor, bank);
if(!ret) {
ret = SCCB_Write(sensor->slv_addr, reg, value);
}
return ret;
}
static int set_reg_bits(sensor_t *sensor, uint8_t bank, uint8_t reg, uint8_t offset, uint8_t mask, uint8_t value)
{
int ret = 0;
uint8_t c_value, new_value;
ret = set_bank(sensor, bank);
if(ret) {
return ret;
}
c_value = SCCB_Read(sensor->slv_addr, reg);
new_value = (c_value & ~(mask << offset)) | ((value & mask) << offset);
ret = SCCB_Write(sensor->slv_addr, reg, new_value);
return ret;
}
//Function is not needed currently
#if 0
static uint8_t get_reg_bits(sensor_t *sensor, uint8_t bank, uint8_t reg, uint8_t offset, uint8_t mask)
{
uint8_t ret = 0;
if(set_bank(sensor, bank)){
return ret;
}
ret = (SCCB_Read(sensor->slv_addr, reg) >> offset) & mask;
return ret;
}
#endif
static int write_reg_bits(sensor_t *sensor, uint8_t bank, uint8_t reg, uint8_t mask, int enable)
{
return set_reg_bits(sensor, bank, reg, 0, mask, enable?mask:0);
}
#define WRITE_REGS_OR_RETURN(regs) ret = write_regs(sensor, regs); if(ret){return ret;}
#define WRITE_REG_OR_RETURN(bank, reg, val) ret = write_reg(sensor, bank, reg, val); if(ret){return ret;}
#define SET_REG_BITS_OR_RETURN(bank, reg, offset, mask, val) ret = set_reg_bits(sensor, bank, reg, offset, mask, val); if(ret){return ret;}
static int reset(sensor_t *sensor)
{
int ret = 0;
WRITE_REG_OR_RETURN(BANK_SENSOR, COM7, COM7_SRST);
vTaskDelay(10 / portTICK_PERIOD_MS);
WRITE_REGS_OR_RETURN(ov2640_settings_cif);
return ret;
}
static int set_pixformat(sensor_t *sensor, pixformat_t pixformat)
{
int ret = 0;
sensor->pixformat = pixformat;
switch (pixformat) {
case PIXFORMAT_RGB565:
case PIXFORMAT_RGB888:
WRITE_REGS_OR_RETURN(ov2640_settings_rgb565);
break;
case PIXFORMAT_YUV422:
case PIXFORMAT_GRAYSCALE:
WRITE_REGS_OR_RETURN(ov2640_settings_yuv422);
break;
case PIXFORMAT_JPEG:
WRITE_REGS_OR_RETURN(ov2640_settings_jpeg3);
break;
default:
ret = -1;
break;
}
if(!ret) {
vTaskDelay(10 / portTICK_PERIOD_MS);
}
return ret;
}
//Functions are not needed currently
#if 0
//Set the sensor output window
int set_output_window(sensor_t *sensor, uint16_t x, uint16_t y, uint16_t width, uint16_t height)
{
int ret = 0;
uint16_t endx, endy;
uint8_t com1, reg32;
endy = y + height / 2;
com1 = read_reg(sensor, BANK_SENSOR, COM1);
WRITE_REG_OR_RETURN(BANK_SENSOR, COM1, (com1 & 0XF0) | (((endy & 0X03) << 2) | (y & 0X03)));
WRITE_REG_OR_RETURN(BANK_SENSOR, VSTART, y >> 2);
WRITE_REG_OR_RETURN(BANK_SENSOR, VSTOP, endy >> 2);
endx = x + width / 2;
reg32 = read_reg(sensor, BANK_SENSOR, REG32);
WRITE_REG_OR_RETURN(BANK_SENSOR, REG32, (reg32 & 0XC0) | (((endx & 0X07) << 3) | (x & 0X07)));
WRITE_REG_OR_RETURN(BANK_SENSOR, HSTART, x >> 3);
WRITE_REG_OR_RETURN(BANK_SENSOR, HSTOP, endx >> 3);
return ret;
}
// Set the image output size (final output resolution)
int set_output_size(sensor_t *sensor, uint16_t width, uint16_t height)
{
int ret = 0;
uint16_t h, w;
if(width % 4) {
return -1;
}
if(height % 4 ) {
return -2;
}
w = width / 4;
h = height / 4;
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, RESET_DVP);
WRITE_REG_OR_RETURN(BANK_DSP, ZMOW, w & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, ZMOH, h & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, ZMHH, ((w >> 8) & 0X03) | ((h >> 6) & 0X04));
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0X00);
return ret;
}
//Set the image window size >= output size
int set_window_size(sensor_t *sensor, uint16_t x, uint16_t y, uint16_t width, uint16_t height)
{
int ret = 0;
uint16_t w, h;
if(width % 4) {
return -1;
}
if(height % 4) {
return -2;
}
w = width / 4;
h = height / 4;
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, RESET_DVP);
WRITE_REG_OR_RETURN(BANK_DSP, HSIZE, w & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, VSIZE, h & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, XOFFL, x & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, YOFFL, y & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, VHYX, ((h >> 1) & 0X80) | ((y >> 4) & 0X70) | ((w >> 5) & 0X08) | ((x >> 8) & 0X07));
WRITE_REG_OR_RETURN(BANK_DSP, TEST, (w >> 2) & 0X80);
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0X00);
return ret;
}
//Set the sensor resolution (UXGA, SVGA, CIF)
int set_image_size(sensor_t *sensor, uint16_t width, uint16_t height)
{
int ret = 0;
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, RESET_DVP);
WRITE_REG_OR_RETURN(BANK_DSP, HSIZE8, (width >> 3) & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, VSIZE8, (height >> 3) & 0XFF);
WRITE_REG_OR_RETURN(BANK_DSP, SIZEL, ((width & 0X07) << 3) | ((width >> 4) & 0X80) | (height & 0X07));
//WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0X00);
return ret;
}
#endif
static int set_framesize(sensor_t *sensor, framesize_t framesize)
{
int ret = 0;
uint16_t w = resolution[framesize][0];
uint16_t h = resolution[framesize][1];
const uint8_t (*regs)[2];
sensor->framesize = framesize;
if (framesize <= FRAMESIZE_CIF) {
regs = ov2640_settings_to_cif;
} else if (framesize <= FRAMESIZE_SVGA) {
regs = ov2640_settings_to_svga;
} else {
regs = ov2640_settings_to_uxga;
}
WRITE_REG_OR_RETURN(BANK_DSP, R_BYPASS, R_BYPASS_DSP_BYPAS);
WRITE_REGS_OR_RETURN(regs);
WRITE_REG_OR_RETURN(BANK_DSP, ZMOW, (w>>2)&0xFF); // OUTW[7:0] (real/4)
WRITE_REG_OR_RETURN(BANK_DSP, ZMOH, (h>>2)&0xFF); // OUTH[7:0] (real/4)
WRITE_REG_OR_RETURN(BANK_DSP, ZMHH, ((h>>8)&0x04)|((w>>10)&0x03)); // OUTH[8]/OUTW[9:8]
WRITE_REG_OR_RETURN(BANK_DSP, RESET, 0x00);
WRITE_REG_OR_RETURN(BANK_DSP, R_BYPASS, R_BYPASS_DSP_EN);
vTaskDelay(10 / portTICK_PERIOD_MS);
//required when changing resolution
set_pixformat(sensor, sensor->pixformat);
return ret;
}
static int set_contrast(sensor_t *sensor, int level)
{
int ret=0;
level += 3;
if (level <= 0 || level > NUM_CONTRAST_LEVELS) {
return -1;
}
for (int i=0; i<7; i++) {
WRITE_REG_OR_RETURN(BANK_DSP, contrast_regs[0][i], contrast_regs[level][i]);
}
return ret;
}
static int set_brightness(sensor_t *sensor, int level)
{
int ret=0;
level += 3;
if (level <= 0 || level > NUM_BRIGHTNESS_LEVELS) {
return -1;
}
for (int i=0; i<5; i++) {
WRITE_REG_OR_RETURN(BANK_DSP, brightness_regs[0][i], brightness_regs[level][i]);
}
return ret;
}
static int set_saturation(sensor_t *sensor, int level)
{
int ret=0;
level += 3;
if (level <= 0 || level > NUM_SATURATION_LEVELS) {
return -1;
}
for (int i=0; i<5; i++) {
WRITE_REG_OR_RETURN(BANK_DSP, saturation_regs[0][i], saturation_regs[level][i]);
}
return ret;
}
static int set_special_effect(sensor_t *sensor, int effect)
{
int ret=0;
effect++;
if (effect <= 0 || effect > NUM_SPECIAL_EFFECTS) {
return -1;
}
for (int i=0; i<5; i++) {
WRITE_REG_OR_RETURN(BANK_DSP, special_effects_regs[0][i], special_effects_regs[effect][i]);
}
return ret;
}
static int set_wb_mode(sensor_t *sensor, int mode)
{
int ret=0;
if (mode < 0 || mode > NUM_WB_MODES) {
return -1;
}
SET_REG_BITS_OR_RETURN(BANK_DSP, 0XC7, 6, 1, mode?1:0);
if(mode) {
for (int i=0; i<3; i++) {
WRITE_REG_OR_RETURN(BANK_DSP, wb_modes_regs[0][i], wb_modes_regs[mode][i]);
}
}
return ret;
}
static int set_ae_level(sensor_t *sensor, int level)
{
int ret=0;
level += 3;
if (level <= 0 || level > NUM_AE_LEVELS) {
return -1;
}
for (int i=0; i<3; i++) {
WRITE_REG_OR_RETURN(BANK_SENSOR, ae_levels_regs[0][i], ae_levels_regs[level][i]);
}
return ret;
}
static int set_agc_gain(sensor_t *sensor, int gain)
{
const uint8_t gain_tbl[31] = {
0x00, 0x10, 0x18, 0x30, 0x34, 0x38, 0x3C, 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, 0x7E, 0xF0,
0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
};
if(gain < 0) {
gain = 0;
} else if(gain > 30) {
gain = 30;
}
return write_reg(sensor, BANK_SENSOR, GAIN, gain_tbl[gain]);
}
static int set_quality(sensor_t *sensor, int qs)
{
return write_reg(sensor, BANK_DSP, QS, qs);
}
static int set_colorbar(sensor_t *sensor, int enable)
{
return write_reg_bits(sensor, BANK_SENSOR, COM7, COM7_COLOR_BAR, enable);
}
static int set_gainceiling_sensor(sensor_t *sensor, gainceiling_t gainceiling)
{
return write_reg(sensor, BANK_SENSOR, COM9, COM9_AGC_SET(gainceiling));
}
static int set_agc_sensor(sensor_t *sensor, int enable)
{
return write_reg_bits(sensor, BANK_SENSOR, COM8, COM8_AGC_EN, enable);
}
static int set_aec_sensor(sensor_t *sensor, int enable)
{
return write_reg_bits(sensor, BANK_SENSOR, COM8, COM8_AEC_EN, enable);
}
static int set_hmirror_sensor(sensor_t *sensor, int enable)
{
return write_reg_bits(sensor, BANK_SENSOR, REG04, REG04_HFLIP_IMG, enable);
}
static int set_vflip_sensor(sensor_t *sensor, int enable)
{
return write_reg_bits(sensor, BANK_SENSOR, REG04, REG04_VFLIP_IMG, enable);
}
static int set_aec_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL0, 6, 1, enable?0:1);
}
static int set_raw_gma_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL1, 5, 1, enable?1:0);
}
static int set_awb_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL1, 3, 1, enable?1:0);
}
static int set_awb_gain_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL1, 2, 1, enable?1:0);
}
static int set_lenc_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL1, 1, 1, enable?1:0);
}
static int set_pre_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL1, 0, 1, enable?1:0);
}
static int set_dcw_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL2, 5, 1, enable?1:0);
}
static int set_bpc_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL3, 7, 1, enable?1:0);
}
static int set_wpc_dsp(sensor_t *sensor, int enable)
{
return set_reg_bits(sensor, BANK_DSP, CTRL3, 6, 1, enable?1:0);
}
static int set_aec_value(sensor_t *sensor, int value)
{
if(value < 0) {
value = 0;
} else if(value > 0xFFFF) {
value = 0xFFFF;
}
return set_reg_bits(sensor, BANK_SENSOR, REG04, 0, 3, value & 0x3)
|| write_reg(sensor, BANK_SENSOR, AEC, (value >> 2) & 0xFF)
|| set_reg_bits(sensor, BANK_SENSOR, REG45, 0, 0x3F, value >> 10);
}
int ov2640_init(sensor_t *sensor)
{
sensor->reset = reset;
sensor->set_pixformat = set_pixformat;
sensor->set_framesize = set_framesize;
sensor->set_contrast = set_contrast;
sensor->set_brightness= set_brightness;
sensor->set_saturation= set_saturation;
sensor->set_quality = set_quality;
sensor->set_colorbar = set_colorbar;
sensor->set_gainceiling = set_gainceiling_sensor;
sensor->set_gain_ctrl = set_agc_sensor;
sensor->set_exposure_ctrl = set_aec_sensor;
sensor->set_hmirror = set_hmirror_sensor;
sensor->set_vflip = set_vflip_sensor;
sensor->set_whitebal = set_awb_dsp;
sensor->set_aec2 = set_aec_dsp;
sensor->set_aec_value = set_aec_value;
sensor->set_special_effect = set_special_effect;
sensor->set_wb_mode = set_wb_mode;
sensor->set_ae_level = set_ae_level;
sensor->set_dcw = set_dcw_dsp;
sensor->set_bpc = set_bpc_dsp;
sensor->set_wpc = set_wpc_dsp;
sensor->set_awb_gain = set_awb_gain_dsp;
sensor->set_agc_gain = set_agc_gain;
sensor->set_raw_gma = set_raw_gma_dsp;
sensor->set_lenc = set_lenc_dsp;
sensor->set_pre = set_pre_dsp;
return 0;
}

309
sensors/ov7725.c Executable file
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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV7725 driver.
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stdio.h>
#include "sccb.h"
#include "ov7725.h"
#include "ov7725_regs.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#if defined(ARDUINO_ARCH_ESP32) && defined(CONFIG_ARDUHAL_ESP_LOG)
#include "esp32-hal-log.h"
#else
#include "esp_log.h"
static const char* TAG = "ov7725";
#endif
static const uint8_t default_regs[][2] = {
{COM3, COM3_SWAP_YUV},
{COM7, COM7_RES_QVGA | COM7_FMT_YUV},
{COM4, 0x01}, /* bypass PLL */
{CLKRC, 0xC0}, /* Res/Bypass pre-scalar */
// QVGA Window Size
{HSTART, 0x3F},
{HSIZE, 0x50},
{VSTART, 0x03},
{VSIZE, 0x78},
{HREF, 0x00},
// Scale down to QVGA Resolution
{HOUTSIZE, 0x50},
{VOUTSIZE, 0x78},
{COM12, 0x03},
{EXHCH, 0x00},
{TGT_B, 0x7F},
{FIXGAIN, 0x09},
{AWB_CTRL0, 0xE0},
{DSP_CTRL1, 0xFF},
{DSP_CTRL2, DSP_CTRL2_VDCW_EN | DSP_CTRL2_HDCW_EN | DSP_CTRL2_HZOOM_EN | DSP_CTRL2_VZOOM_EN},
{DSP_CTRL3, 0x00},
{DSP_CTRL4, 0x00},
{DSPAUTO, 0xFF},
{COM8, 0xF0},
{COM6, 0xC5},
{COM9, 0x11},
{COM10, COM10_VSYNC_NEG | COM10_PCLK_MASK}, //Invert VSYNC and MASK PCLK
{BDBASE, 0x7F},
{DBSTEP, 0x03},
{AEW, 0x96},
{AEB, 0x64},
{VPT, 0xA1},
{EXHCL, 0x00},
{AWB_CTRL3, 0xAA},
{COM8, 0xFF},
//Gamma
{GAM1, 0x0C},
{GAM2, 0x16},
{GAM3, 0x2A},
{GAM4, 0x4E},
{GAM5, 0x61},
{GAM6, 0x6F},
{GAM7, 0x7B},
{GAM8, 0x86},
{GAM9, 0x8E},
{GAM10, 0x97},
{GAM11, 0xA4},
{GAM12, 0xAF},
{GAM13, 0xC5},
{GAM14, 0xD7},
{GAM15, 0xE8},
{SLOP, 0x20},
{EDGE1, 0x05},
{EDGE2, 0x03},
{EDGE3, 0x00},
{DNSOFF, 0x01},
{MTX1, 0xB0},
{MTX2, 0x9D},
{MTX3, 0x13},
{MTX4, 0x16},
{MTX5, 0x7B},
{MTX6, 0x91},
{MTX_CTRL, 0x1E},
{BRIGHTNESS, 0x08},
{CONTRAST, 0x30},
{UVADJ0, 0x81},
{SDE, (SDE_CONT_BRIGHT_EN | SDE_SATURATION_EN)},
// For 30 fps/60Hz
{DM_LNL, 0x00},
{DM_LNH, 0x00},
{BDBASE, 0x7F},
{DBSTEP, 0x03},
// Lens Correction, should be tuned with real camera module
{LC_RADI, 0x10},
{LC_COEF, 0x10},
{LC_COEFB, 0x14},
{LC_COEFR, 0x17},
{LC_CTR, 0x05},
{COM5, 0xF5}, //0x65
{0x00, 0x00},
};
static int reset(sensor_t *sensor)
{
int i=0;
const uint8_t (*regs)[2];
// Reset all registers
SCCB_Write(sensor->slv_addr, COM7, COM7_RESET);
// Delay 10 ms
vTaskDelay(10 / portTICK_PERIOD_MS);
// Write default regsiters
for (i=0, regs = default_regs; regs[i][0]; i++) {
SCCB_Write(sensor->slv_addr, regs[i][0], regs[i][1]);
}
// Delay
vTaskDelay(30 / portTICK_PERIOD_MS);
return 0;
}
static int set_pixformat(sensor_t *sensor, pixformat_t pixformat)
{
int ret=0;
// Read register COM7
uint8_t reg = SCCB_Read(sensor->slv_addr, COM7);
switch (pixformat) {
case PIXFORMAT_RGB565:
reg = COM7_SET_RGB(reg, COM7_FMT_RGB565);
break;
case PIXFORMAT_YUV422:
case PIXFORMAT_GRAYSCALE:
reg = COM7_SET_FMT(reg, COM7_FMT_YUV);
break;
default:
return -1;
}
// Write back register COM7
ret = SCCB_Write(sensor->slv_addr, COM7, reg);
// Delay
vTaskDelay(30 / portTICK_PERIOD_MS);
return ret;
}
static int set_framesize(sensor_t *sensor, framesize_t framesize)
{
int ret=0;
uint16_t w = resolution[framesize][0];
uint16_t h = resolution[framesize][1];
// Write MSBs
ret |= SCCB_Write(sensor->slv_addr, HOUTSIZE, w>>2);
ret |= SCCB_Write(sensor->slv_addr, VOUTSIZE, h>>1);
// Write LSBs
ret |= SCCB_Write(sensor->slv_addr, EXHCH, ((w&0x3) | ((h&0x1) << 2)));
if (framesize < FRAMESIZE_VGA) {
// Enable auto-scaling/zooming factors
ret |= SCCB_Write(sensor->slv_addr, DSPAUTO, 0xFF);
} else {
// Disable auto-scaling/zooming factors
ret |= SCCB_Write(sensor->slv_addr, DSPAUTO, 0xF3);
// Clear auto-scaling/zooming factors
ret |= SCCB_Write(sensor->slv_addr, SCAL0, 0x00);
ret |= SCCB_Write(sensor->slv_addr, SCAL1, 0x00);
ret |= SCCB_Write(sensor->slv_addr, SCAL2, 0x00);
}
// Delay
vTaskDelay(30 / portTICK_PERIOD_MS);
return ret;
}
static int set_colorbar(sensor_t *sensor, int enable)
{
int ret=0;
uint8_t reg;
// Read reg COM3
reg = SCCB_Read(sensor->slv_addr, COM3);
// Enable colorbar test pattern output
reg = COM3_SET_CBAR(reg, enable);
// Write back COM3
ret |= SCCB_Write(sensor->slv_addr, COM3, reg);
// Read reg DSP_CTRL3
reg = SCCB_Read(sensor->slv_addr, DSP_CTRL3);
// Enable DSP colorbar output
reg = DSP_CTRL3_SET_CBAR(reg, enable);
// Write back DSP_CTRL3
ret |= SCCB_Write(sensor->slv_addr, DSP_CTRL3, reg);
return ret;
}
static int set_whitebal(sensor_t *sensor, int enable)
{
// Read register COM8
uint8_t reg = SCCB_Read(sensor->slv_addr, COM8);
// Set white bal on/off
reg = COM8_SET_AWB(reg, enable);
// Write back register COM8
return SCCB_Write(sensor->slv_addr, COM8, reg);
}
static int set_gain_ctrl(sensor_t *sensor, int enable)
{
// Read register COM8
uint8_t reg = SCCB_Read(sensor->slv_addr, COM8);
// Set white bal on/off
reg = COM8_SET_AGC(reg, enable);
// Write back register COM8
return SCCB_Write(sensor->slv_addr, COM8, reg);
}
static int set_exposure_ctrl(sensor_t *sensor, int enable)
{
// Read register COM8
uint8_t reg = SCCB_Read(sensor->slv_addr, COM8);
// Set white bal on/off
reg = COM8_SET_AEC(reg, enable);
// Write back register COM8
return SCCB_Write(sensor->slv_addr, COM8, reg);
}
static int set_hmirror(sensor_t *sensor, int enable)
{
// Read register COM3
uint8_t reg = SCCB_Read(sensor->slv_addr, COM3);
// Set mirror on/off
reg = COM3_SET_MIRROR(reg, enable);
// Write back register COM3
return SCCB_Write(sensor->slv_addr, COM3, reg);
}
static int set_vflip(sensor_t *sensor, int enable)
{
// Read register COM3
uint8_t reg = SCCB_Read(sensor->slv_addr, COM3);
// Set mirror on/off
reg = COM3_SET_FLIP(reg, enable);
// Write back register COM3
return SCCB_Write(sensor->slv_addr, COM3, reg);
}
int ov7725_init(sensor_t *sensor)
{
// Set function pointers
sensor->reset = reset;
sensor->set_pixformat = set_pixformat;
sensor->set_framesize = set_framesize;
sensor->set_colorbar = set_colorbar;
sensor->set_whitebal = set_whitebal;
sensor->set_gain_ctrl = set_gain_ctrl;
sensor->set_exposure_ctrl = set_exposure_ctrl;
sensor->set_hmirror = set_hmirror;
sensor->set_vflip = set_vflip;
// Retrieve sensor's signature
sensor->id.MIDH = SCCB_Read(sensor->slv_addr, REG_MIDH);
sensor->id.MIDL = SCCB_Read(sensor->slv_addr, REG_MIDL);
sensor->id.PID = SCCB_Read(sensor->slv_addr, REG_PID);
sensor->id.VER = SCCB_Read(sensor->slv_addr, REG_VER);
return 0;
}

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sensors/private_include/ov2640.h Executable file
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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV2640 driver.
*
*/
#ifndef __OV2640_H__
#define __OV2640_H__
#include "sensor.h"
int ov2640_init(sensor_t *sensor);
#endif // __OV2640_H__

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sensors/private_include/ov2640_regs.h Executable file
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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV2640 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
/* DSP register bank FF=0x00*/
#define R_BYPASS 0x05
#define QS 0x44
#define CTRLI 0x50
#define HSIZE 0x51
#define VSIZE 0x52
#define XOFFL 0x53
#define YOFFL 0x54
#define VHYX 0x55
#define DPRP 0x56
#define TEST 0x57
#define ZMOW 0x5A
#define ZMOH 0x5B
#define ZMHH 0x5C
#define BPADDR 0x7C
#define BPDATA 0x7D
#define CTRL2 0x86
#define CTRL3 0x87
#define SIZEL 0x8C
#define HSIZE8 0xC0
#define VSIZE8 0xC1
#define CTRL0 0xC2
#define CTRL1 0xC3
#define R_DVP_SP 0xD3
#define IMAGE_MODE 0xDA
#define RESET 0xE0
#define MS_SP 0xF0
#define SS_ID 0xF7
#define SS_CTRL 0xF7
#define MC_BIST 0xF9
#define MC_AL 0xFA
#define MC_AH 0xFB
#define MC_D 0xFC
#define P_CMD 0xFD
#define P_STATUS 0xFE
#define BANK_SEL 0xFF
#define CTRLI_LP_DP 0x80
#define CTRLI_ROUND 0x40
#define CTRL0_AEC_EN 0x80
#define CTRL0_AEC_SEL 0x40
#define CTRL0_STAT_SEL 0x20
#define CTRL0_VFIRST 0x10
#define CTRL0_YUV422 0x08
#define CTRL0_YUV_EN 0x04
#define CTRL0_RGB_EN 0x02
#define CTRL0_RAW_EN 0x01
#define CTRL2_DCW_EN 0x20
#define CTRL2_SDE_EN 0x10
#define CTRL2_UV_ADJ_EN 0x08
#define CTRL2_UV_AVG_EN 0x04
#define CTRL2_CMX_EN 0x01
#define CTRL3_BPC_EN 0x80
#define CTRL3_WPC_EN 0x40
#define R_DVP_SP_AUTO_MODE 0x80
#define R_BYPASS_DSP_EN 0x00
#define R_BYPASS_DSP_BYPAS 0x01
#define IMAGE_MODE_Y8_DVP_EN 0x40
#define IMAGE_MODE_JPEG_EN 0x10
#define IMAGE_MODE_YUV422 0x00
#define IMAGE_MODE_RAW10 0x04
#define IMAGE_MODE_RGB565 0x08
#define IMAGE_MODE_HREF_VSYNC 0x02
#define IMAGE_MODE_LBYTE_FIRST 0x01
#define RESET_MICROC 0x40
#define RESET_SCCB 0x20
#define RESET_JPEG 0x10
#define RESET_DVP 0x04
#define RESET_IPU 0x02
#define RESET_CIF 0x01
#define MC_BIST_RESET 0x80
#define MC_BIST_BOOT_ROM_SEL 0x40
#define MC_BIST_12KB_SEL 0x20
#define MC_BIST_12KB_MASK 0x30
#define MC_BIST_512KB_SEL 0x08
#define MC_BIST_512KB_MASK 0x0C
#define MC_BIST_BUSY_BIT_R 0x02
#define MC_BIST_MC_RES_ONE_SH_W 0x02
#define MC_BIST_LAUNCH 0x01
typedef enum {
BANK_DSP, BANK_SENSOR, BANK_MAX
} ov2640_bank_t;
/* Sensor register bank FF=0x01*/
#define GAIN 0x00
#define COM1 0x03
#define REG04 0x04
#define REG08 0x08
#define COM2 0x09
#define REG_PID 0x0A
#define REG_VER 0x0B
#define COM3 0x0C
#define COM4 0x0D
#define AEC 0x10
#define CLKRC 0x11
#define COM7 0x12
#define COM8 0x13
#define COM9 0x14 /* AGC gain ceiling */
#define COM10 0x15
#define HSTART 0x17
#define HSTOP 0x18
#define VSTART 0x19
#define VSTOP 0x1A
#define MIDH 0x1C
#define MIDL 0x1D
#define AEW 0x24
#define AEB 0x25
#define VV 0x26
#define REG2A 0x2A
#define FRARL 0x2B
#define ADDVSL 0x2D
#define ADDVSH 0x2E
#define YAVG 0x2F
#define HSDY 0x30
#define HEDY 0x31
#define REG32 0x32
#define ARCOM2 0x34
#define REG45 0x45
#define FLL 0x46
#define FLH 0x47
#define COM19 0x48
#define ZOOMS 0x49
#define COM22 0x4B
#define COM25 0x4E
#define BD50 0x4F
#define BD60 0x50
#define REG5D 0x5D
#define REG5E 0x5E
#define REG5F 0x5F
#define REG60 0x60
#define HISTO_LOW 0x61
#define HISTO_HIGH 0x62
#define REG04_DEFAULT 0x28
#define REG04_HFLIP_IMG 0x80
#define REG04_VFLIP_IMG 0x40
#define REG04_VREF_EN 0x10
#define REG04_HREF_EN 0x08
#define REG04_SET(x) (REG04_DEFAULT|x)
#define COM2_STDBY 0x10
#define COM2_OUT_DRIVE_1x 0x00
#define COM2_OUT_DRIVE_2x 0x01
#define COM2_OUT_DRIVE_3x 0x02
#define COM2_OUT_DRIVE_4x 0x03
#define COM3_DEFAULT 0x38
#define COM3_BAND_50Hz 0x04
#define COM3_BAND_60Hz 0x00
#define COM3_BAND_AUTO 0x02
#define COM3_BAND_SET(x) (COM3_DEFAULT|x)
#define COM7_SRST 0x80
#define COM7_RES_UXGA 0x00 /* UXGA */
#define COM7_RES_SVGA 0x40 /* SVGA */
#define COM7_RES_CIF 0x20 /* CIF */
#define COM7_ZOOM_EN 0x04 /* Enable Zoom */
#define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
#define COM8_DEFAULT 0xC0
#define COM8_BNDF_EN 0x20 /* Enable Banding filter */
#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
#define COM8_SET(x) (COM8_DEFAULT|x)
#define COM9_DEFAULT 0x08
#define COM9_AGC_GAIN_2x 0x00 /* AGC: 2x */
#define COM9_AGC_GAIN_4x 0x01 /* AGC: 4x */
#define COM9_AGC_GAIN_8x 0x02 /* AGC: 8x */
#define COM9_AGC_GAIN_16x 0x03 /* AGC: 16x */
#define COM9_AGC_GAIN_32x 0x04 /* AGC: 32x */
#define COM9_AGC_GAIN_64x 0x05 /* AGC: 64x */
#define COM9_AGC_GAIN_128x 0x06 /* AGC: 128x */
#define COM9_AGC_SET(x) (COM9_DEFAULT|(x<<5))
#define COM10_HREF_EN 0x80 /* HSYNC changes to HREF */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x20 /* PCLK output option: free running PCLK */
#define COM10_PCLK_EDGE 0x10 /* Data is updated at the rising edge of PCLK */
#define COM10_HREF_NEG 0x08 /* HREF negative */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_HSYNC_NEG 0x01 /* HSYNC negative */
#define CTRL1_AWB 0x08 /* Enable AWB */
#define VV_AGC_TH_SET(h,l) ((h<<4)|(l&0x0F))
#define REG32_UXGA 0x36
#define REG32_SVGA 0x09
#define REG32_CIF 0x89
#define CLKRC_2X 0x80
#endif //__REG_REGS_H__

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _OV2640_SETTINGS_H_
#define _OV2640_SETTINGS_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "ov2640_regs.h"
// 30fps@24MHz
const DRAM_ATTR uint8_t ov2640_settings_cif[][2] = {
{BANK_SEL, BANK_DSP},
{0x2c, 0xff},
{0x2e, 0xdf},
{BANK_SEL, BANK_SENSOR},
{0x3c, 0x32},
{CLKRC, 0x01},
{COM2, COM2_OUT_DRIVE_3x},
{REG04, REG04_DEFAULT},
{COM8, COM8_DEFAULT | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN},
{COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
{0x2c, 0x0c},
{0x33, 0x78},
{0x3a, 0x33},
{0x3b, 0xfB},
{0x3e, 0x00},
{0x43, 0x11},
{0x16, 0x10},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{ARCOM2, 0xc0},
{0x06, 0x88},
{0x07, 0xc0},
{COM4, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0x4a, 0x81},
{0x21, 0x99},
{AEW, 0x40},
{AEB, 0x38},
{VV, VV_AGC_TH_SET(8,2)},
{0x5c, 0x00},
{0x63, 0x00},
{HISTO_LOW, 0x70},
{HISTO_HIGH, 0x80},
{0x7c, 0x05},
{0x20, 0x80},
{0x28, 0x30},
{0x6c, 0x00},
{0x6d, 0x80},
{0x6e, 0x00},
{0x70, 0x02},
{0x71, 0x94},
{0x73, 0xc1},
{0x3d, 0x34},
{0x5a, 0x57},
{BD50, 0xbb},
{BD60, 0x9c},
{COM7, COM7_RES_CIF},
{HSTART, 0x11},
{HSTOP, 0x43},
{VSTART, 0x00},
{VSTOP, 0x25},
{REG32, 0x89},
{0x37, 0xc0},
{BD50, 0xca},
{BD60, 0xa8},
{0x6d, 0x00},
{0x3d, 0x38},
{BANK_SEL, BANK_DSP},
{0xe5, 0x7f},
{MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL},
{0x41, 0x24},
{RESET, RESET_JPEG | RESET_DVP},
{0x76, 0xff},
{0x33, 0xa0},
{0x42, 0x20},
{0x43, 0x18},
{0x4c, 0x00},
{CTRL3, CTRL3_WPC_EN | 0x10 },
{0x88, 0x3f},
{0xd7, 0x03},
{0xd9, 0x10},
{R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x02},
{0xc8, 0x08},
{0xc9, 0x80},
{BPADDR, 0x00},
{BPDATA, 0x00},
{BPADDR, 0x03},
{BPDATA, 0x48},
{BPDATA, 0x48},
{BPADDR, 0x08},
{BPDATA, 0x20},
{BPDATA, 0x10},
{BPDATA, 0x0e},
{0x90, 0x00},
{0x91, 0x0e},
{0x91, 0x1a},
{0x91, 0x31},
{0x91, 0x5a},
{0x91, 0x69},
{0x91, 0x75},
{0x91, 0x7e},
{0x91, 0x88},
{0x91, 0x8f},
{0x91, 0x96},
{0x91, 0xa3},
{0x91, 0xaf},
{0x91, 0xc4},
{0x91, 0xd7},
{0x91, 0xe8},
{0x91, 0x20},
{0x92, 0x00},
{0x93, 0x06},
{0x93, 0xe3},
{0x93, 0x05},
{0x93, 0x05},
{0x93, 0x00},
{0x93, 0x04},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x96, 0x00},
{0x97, 0x08},
{0x97, 0x19},
{0x97, 0x02},
{0x97, 0x0c},
{0x97, 0x24},
{0x97, 0x30},
{0x97, 0x28},
{0x97, 0x26},
{0x97, 0x02},
{0x97, 0x98},
{0x97, 0x80},
{0x97, 0x00},
{0x97, 0x00},
{0xa4, 0x00},
{0xa8, 0x00},
{0xc5, 0x11},
{0xc6, 0x51},
{0xbf, 0x80},
{0xc7, 0x10},
{0xb6, 0x66},
{0xb8, 0xA5},
{0xb7, 0x64},
{0xb9, 0x7C},
{0xb3, 0xaf},
{0xb4, 0x97},
{0xb5, 0xFF},
{0xb0, 0xC5},
{0xb1, 0x94},
{0xb2, 0x0f},
{0xc4, 0x5c},
{CTRL1, 0xfd},
{0x7f, 0x00},
{0xe5, 0x1f},
{0xe1, 0x67},
{0xdd, 0x7f},
{IMAGE_MODE, 0x00},
{RESET, 0x00},
{R_BYPASS, R_BYPASS_DSP_EN},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_to_cif[][2] = {
{BANK_SEL, BANK_SENSOR},
{COM7, COM7_RES_CIF},
//Set the sensor output window
{COM1, 0x0A},
{REG32, REG32_CIF},
{HSTART, 0x11},
{HSTOP, 0x43},
{VSTART, 0x00},
{VSTOP, 0x25},
{CLKRC, 0x01},
{BD50, 0xca},
{BD60, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x3d, 0x38},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{ARCOM2, 0xc0},
{0x06, 0x88},
{0x07, 0xc0},
{COM4, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
//Set the sensor resolution (UXGA, SVGA, CIF)
{HSIZE8, 0x32},
{VSIZE8, 0x25},
{SIZEL, 0x00},
//Set the image window size >= output size
{HSIZE, 0x64},
{VSIZE, 0x4a},
{XOFFL, 0x00},
{YOFFL, 0x00},
{VHYX, 0x00},
{TEST, 0x00},
{CTRL2, CTRL2_DCW_EN | 0x1D},
{CTRLI, CTRLI_LP_DP | 0x00},
{R_DVP_SP, 0x82},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_to_svga[][2] = {
{BANK_SEL, BANK_SENSOR},
{COM7, COM7_RES_SVGA},
//Set the sensor output window
{COM1, 0x0A},
{REG32, REG32_SVGA},
{HSTART, 0x11},
{HSTOP, 0x43},
{VSTART, 0x00},
{VSTOP, 0x4b},
{CLKRC, 0x01},
{0x37, 0xc0},
{BD50, 0xca},
{BD60, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x3d, 0x38},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{ARCOM2, 0xc0},
{0x06, 0x88},
{0x07, 0xc0},
{COM4, 0x87},
{0x0e, 0x41},
{0x42, 0x03},
{0x4c, 0x00},
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
//Set the sensor resolution (UXGA, SVGA, CIF)
{HSIZE8, 0x64},
{VSIZE8, 0x4B},
{SIZEL, 0x00},
//Set the image window size >= output size
{HSIZE, 0xC8},
{VSIZE, 0x96},
{XOFFL, 0x00},
{YOFFL, 0x00},
{VHYX, 0x00},
{TEST, 0x00},
{CTRL2, CTRL2_DCW_EN | 0x1D},
{CTRLI, CTRLI_LP_DP | 0x00},
{R_DVP_SP, 0x80},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_to_uxga[][2] = {
{BANK_SEL, BANK_SENSOR},
{COM7, COM7_RES_UXGA},
//Set the sensor output window
{COM1, 0x0F},
{REG32, REG32_UXGA},
{HSTART, 0x11},
{HSTOP, 0x75},
{VSTART, 0x01},
{VSTOP, 0x97},
{CLKRC, 0x01},
{0x3d, 0x34},
{BD50, 0xbb},
{BD60, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x39, 0x82},
{0x23, 0x00},
{0x07, 0xc0},
{0x4c, 0x00},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{ARCOM2, 0xa0},
{0x06, 0x02},
{COM4, 0xb7},
{0x0e, 0x01},
{0x42, 0x83},
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
//Set the sensor resolution (UXGA, SVGA, CIF)
{HSIZE8, 0xc8},
{VSIZE8, 0x96},
{SIZEL, 0x00},
//Set the image window size >= output size
{HSIZE, 0x90},
{VSIZE, 0x2c},
{XOFFL, 0x00},
{YOFFL, 0x00},
{VHYX, 0x88},
{TEST, 0x00},
{CTRL2, CTRL2_DCW_EN | 0x1d},
{CTRLI, 0x00},
{R_DVP_SP, 0x82},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_jpeg3[][2] = {
{BANK_SEL, BANK_DSP},
{RESET, RESET_JPEG | RESET_DVP},
{IMAGE_MODE, IMAGE_MODE_JPEG_EN | IMAGE_MODE_HREF_VSYNC},
{0xD7, 0x03},
{0xE1, 0x77},
{0xE5, 0x1F},
{0xD9, 0x10},
{0xDF, 0x80},
{0x33, 0x80},
{0x3C, 0x10},
{R_DVP_SP, 0x04},
{0xEB, 0x30},
{0xDD, 0x7F},
{RESET, 0x00},
{0, 0}
};
static const uint8_t ov2640_settings_yuv422[][2] = {
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
{IMAGE_MODE, IMAGE_MODE_YUV422},
{0xD7, 0x01},
{0xE1, 0x67},
{RESET, 0x00},
{0, 0},
};
static const uint8_t ov2640_settings_rgb565[][2] = {
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
{IMAGE_MODE, IMAGE_MODE_RGB565},
{0xD7, 0x03},
{0xE1, 0x77},
{RESET, 0x00},
{0, 0},
};
#define NUM_BRIGHTNESS_LEVELS (5)
static const uint8_t brightness_regs[NUM_BRIGHTNESS_LEVELS + 1][5] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
{0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
{0x00, 0x04, 0x09, 0x10, 0x00 }, /* -1 */
{0x00, 0x04, 0x09, 0x20, 0x00 }, /* 0 */
{0x00, 0x04, 0x09, 0x30, 0x00 }, /* +1 */
{0x00, 0x04, 0x09, 0x40, 0x00 }, /* +2 */
};
#define NUM_CONTRAST_LEVELS (5)
static const uint8_t contrast_regs[NUM_CONTRAST_LEVELS + 1][7] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA, BPDATA, BPDATA },
{0x00, 0x04, 0x07, 0x20, 0x18, 0x34, 0x06 }, /* -2 */
{0x00, 0x04, 0x07, 0x20, 0x1c, 0x2a, 0x06 }, /* -1 */
{0x00, 0x04, 0x07, 0x20, 0x20, 0x20, 0x06 }, /* 0 */
{0x00, 0x04, 0x07, 0x20, 0x24, 0x16, 0x06 }, /* +1 */
{0x00, 0x04, 0x07, 0x20, 0x28, 0x0c, 0x06 }, /* +2 */
};
#define NUM_SATURATION_LEVELS (5)
static const uint8_t saturation_regs[NUM_SATURATION_LEVELS + 1][5] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
{0x00, 0x02, 0x03, 0x28, 0x28 }, /* -2 */
{0x00, 0x02, 0x03, 0x38, 0x38 }, /* -1 */
{0x00, 0x02, 0x03, 0x48, 0x48 }, /* 0 */
{0x00, 0x02, 0x03, 0x58, 0x58 }, /* +1 */
{0x00, 0x02, 0x03, 0x68, 0x68 }, /* +2 */
};
#define NUM_SPECIAL_EFFECTS (7)
static const uint8_t special_effects_regs[NUM_SPECIAL_EFFECTS + 1][5] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
{0x00, 0X00, 0x05, 0X80, 0X80 }, /* no effect */
{0x00, 0X40, 0x05, 0X80, 0X80 }, /* negative */
{0x00, 0X18, 0x05, 0X80, 0X80 }, /* black and white */
{0x00, 0X18, 0x05, 0X40, 0XC0 }, /* reddish */
{0x00, 0X18, 0x05, 0X40, 0X40 }, /* greenish */
{0x00, 0X18, 0x05, 0XA0, 0X40 }, /* blue */
{0x00, 0X18, 0x05, 0X40, 0XA6 }, /* retro */
};
#define NUM_WB_MODES (4)
static const uint8_t wb_modes_regs[NUM_WB_MODES + 1][3] = {
{0XCC, 0XCD, 0XCE },
{0x5E, 0X41, 0x54 }, /* sunny */
{0x65, 0X41, 0x4F }, /* cloudy */
{0x52, 0X41, 0x66 }, /* office */
{0x42, 0X3F, 0x71 }, /* home */
};
#define NUM_AE_LEVELS (5)
static const uint8_t ae_levels_regs[NUM_AE_LEVELS + 1][3] = {
{ AEW, AEB, VV },
{0x20, 0X18, 0x60 },
{0x34, 0X1C, 0x00 },
{0x3E, 0X38, 0x81 },
{0x48, 0X40, 0x81 },
{0x58, 0X50, 0x92 },
};
#endif /* _OV2640_SETTINGS_H_ */

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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV7725 driver.
*
*/
#ifndef __OV7725_H__
#define __OV7725_H__
#include "sensor.h"
int ov7725_init(sensor_t *sensor);
#endif // __OV7725_H__

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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV2640 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00 /* AGC – Gain control gain setting */
#define BLUE 0x01 /* AWB – Blue channel gain setting */
#define RED 0x02 /* AWB – Red channel gain setting */
#define GREEN 0x03 /* AWB – Green channel gain setting */
#define BAVG 0x05 /* U/B Average Level */
#define GAVG 0x06 /* Y/Gb Average Level */
#define RAVG 0x07 /* V/R Average Level */
#define AECH 0x08 /* Exposure Value – AEC MSBs */
#define COM2 0x09 /* Common Control 2 */
#define COM2_SOFT_SLEEP 0x10 /* Soft sleep mode */
#define COM2_OUT_DRIVE_1x 0x00 /* Output drive capability 1x */
#define COM2_OUT_DRIVE_2x 0x01 /* Output drive capability 2x */
#define COM2_OUT_DRIVE_3x 0x02 /* Output drive capability 3x */
#define COM2_OUT_DRIVE_4x 0x03 /* Output drive capability 4x */
#define REG_PID 0x0A /* Product ID Number MSB */
#define REG_VER 0x0B /* Product ID Number LSB */
#define COM3 0x0C /* Common Control 3 */
#define COM3_VFLIP 0x80 /* Vertical flip image ON/OFF selection */
#define COM3_MIRROR 0x40 /* Horizontal mirror image ON/OFF selection */
#define COM3_SWAP_BR 0x20 /* Swap B/R output sequence in RGB output mode */
#define COM3_SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV output mode */
#define COM3_SWAP_MSB 0x08 /* Swap output MSB/LSB */
#define COM3_TRI_CLOCK 0x04 /* Tri-state option for output clock at power-down period */
#define COM3_TRI_DATA 0x02 /* Tri-state option for output data at power-down period */
#define COM3_COLOR_BAR 0x01 /* Sensor color bar test pattern output enable */
#define COM3_SET_CBAR(r, x) ((r&0xFE)|((x&1)<<0))
#define COM3_SET_MIRROR(r, x) ((r&0xBF)|((x&1)<<6))
#define COM3_SET_FLIP(r, x) ((r&0x7F)|((x&1)<<7))
#define COM4 0x0D /* Common Control 4 */
#define COM4_PLL_BYPASS 0x00 /* Bypass PLL */
#define COM4_PLL_4x 0x40 /* PLL frequency 4x */
#define COM4_PLL_6x 0x80 /* PLL frequency 6x */
#define COM4_PLL_8x 0xc0 /* PLL frequency 8x */
#define COM4_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM4_AEC_1_2 0x10 /* AEC evaluate 1/2 window */
#define COM4_AEC_1_4 0x20 /* AEC evaluate 1/4 window */
#define COM4_AEC_2_3 0x30 /* AEC evaluate 2/3 window */
#define COM5 0x0E /* Common Control 5 */
#define COM5_AFR 0x80 /* Auto frame rate control ON/OFF selection (night mode) */
#define COM5_AFR_SPEED 0x40 /* Auto frame rate control speed selection */
#define COM5_AFR_0 0x00 /* No reduction of frame rate */
#define COM5_AFR_1_2 0x10 /* Max reduction to 1/2 frame rate */
#define COM5_AFR_1_4 0x20 /* Max reduction to 1/4 frame rate */
#define COM5_AFR_1_8 0x30 /* Max reduction to 1/8 frame rate */
#define COM5_AFR_4x 0x04 /* Add frame when AGC reaches 4x gain */
#define COM5_AFR_8x 0x08 /* Add frame when AGC reaches 8x gain */
#define COM5_AFR_16x 0x0c /* Add frame when AGC reaches 16x gain */
#define COM5_AEC_NO_LIMIT 0x01 /* No limit to AEC increase step */
#define COM6 0x0F /* Common Control 6 */
#define COM6_AUTO_WINDOW 0x01 /* Auto window setting ON/OFF selection when format changes */
#define AEC 0x10 /* AEC[7:0] (see register AECH for AEC[15:8]) */
#define CLKRC 0x11 /* Internal Clock */
#define COM7 0x12 /* Common Control 7 */
#define COM7_RESET 0x80 /* SCCB Register Reset */
#define COM7_RES_VGA 0x00 /* Resolution VGA */
#define COM7_RES_QVGA 0x40 /* Resolution QVGA */
#define COM7_BT656 0x20 /* BT.656 protocol ON/OFF */
#define COM7_SENSOR_RAW 0x10 /* Sensor RAW */
#define COM7_FMT_GBR422 0x00 /* RGB output format GBR422 */
#define COM7_FMT_RGB565 0x04 /* RGB output format RGB565 */
#define COM7_FMT_RGB555 0x08 /* RGB output format RGB555 */
#define COM7_FMT_RGB444 0x0C /* RGB output format RGB444 */
#define COM7_FMT_YUV 0x00 /* Output format YUV */
#define COM7_FMT_P_BAYER 0x01 /* Output format Processed Bayer RAW */
#define COM7_FMT_RGB 0x02 /* Output format RGB */
#define COM7_FMT_R_BAYER 0x03 /* Output format Bayer RAW */
#define COM7_SET_FMT(r, x) ((r&0xFC)|((x&0x3)<<0))
#define COM7_SET_RGB(r, x) ((r&0xF0)|(x&0x0C)|COM7_FMT_RGB)
#define COM8 0x13 /* Common Control 8 */
#define COM8_FAST_AUTO 0x80 /* Enable fast AGC/AEC algorithm */
#define COM8_STEP_VSYNC 0x00 /* AEC - Step size limited to vertical blank */
#define COM8_STEP_UNLIMIT 0x40 /* AEC - Step size unlimited step size */
#define COM8_BANDF_EN 0x20 /* Banding filter ON/OFF */
#define COM8_AEC_BANDF 0x10 /* Enable AEC below banding value */
#define COM8_AEC_FINE_EN 0x08 /* Fine AEC ON/OFF control */
#define COM8_AGC_EN 0x04 /* AGC Enable */
#define COM8_AWB_EN 0x02 /* AWB Enable */
#define COM8_AEC_EN 0x01 /* AEC Enable */
#define COM8_SET_AGC(r, x) ((r&0xFB)|((x&0x1)<<2))
#define COM8_SET_AWB(r, x) ((r&0xFD)|((x&0x1)<<1))
#define COM8_SET_AEC(r, x) ((r&0xFE)|((x&0x1)<<0))
#define COM9 0x14 /* Common Control 9 */
#define COM9_HISTO_AVG 0x80 /* Histogram or average based AEC/AGC selection */
#define COM9_AGC_GAIN_2x 0x00 /* Automatic Gain Ceiling 2x */
#define COM9_AGC_GAIN_4x 0x10 /* Automatic Gain Ceiling 4x */
#define COM9_AGC_GAIN_8x 0x20 /* Automatic Gain Ceiling 8x */
#define COM9_AGC_GAIN_16x 0x30 /* Automatic Gain Ceiling 16x */
#define COM9_AGC_GAIN_32x 0x40 /* Automatic Gain Ceiling 32x */
#define COM9_DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
#define COM9_DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
#define COM9_SET_AGC(r, x) ((r&0x8F)|((x&0x07)<<4))
#define COM10 0x15 /* Common Control 10 */
#define COM10_NEGATIVE 0x80 /* Output negative data */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x00 /* PCLK output option: free running PCLK */
#define COM10_PCLK_MASK 0x20 /* PCLK output option: masked during horizontal blank */
#define COM10_PCLK_REV 0x10 /* PCLK reverse */
#define COM10_HREF_REV 0x08 /* HREF reverse */
#define COM10_VSYNC_FALLING 0x00 /* VSYNC changes on falling edge of PCLK */
#define COM10_VSYNC_RISING 0x04 /* VSYNC changes on rising edge of PCLK */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_OUT_RANGE_8 0x01 /* Output data range: Full range */
#define COM10_OUT_RANGE_10 0x00 /* Output data range: Data from [10] to [F0] (8 MSBs) */
#define REG16 0x16 /* Register 16 */
#define REG16_BIT_SHIFT 0x80 /* Bit shift test pattern options */
#define HSTART 0x17 /* Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4]) */
#define HSIZE 0x18 /* Horizontal Sensor Size (2 LSBs are at HREF[1:0]) */
#define VSTART 0x19 /* Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6]) */
#define VSIZE 0x1A /* Vertical Sensor Size (1 LSB is at HREF[2]) */
#define PSHFT 0x1B /* Data Format - Pixel Delay Select */
#define REG_MIDH 0x1C /* Manufacturer ID Byte – High */
#define REG_MIDL 0x1D /* Manufacturer ID Byte – Low */
#define LAEC 0x1F /* Fine AEC Value - defines exposure value less than one row period */
#define COM11 0x20 /* Common Control 11 */
#define COM11_SNGL_FRAME_EN 0x02 /* Single frame ON/OFF selection */
#define COM11_SNGL_XFR_TRIG 0x01 /* Single frame transfer trigger */
#define BDBASE 0x22 /* Banding Filter Minimum AEC Value */
#define DBSTEP 0x23 /* Banding Filter Maximum Step */
#define AEW 0x24 /* AGC/AEC - Stable Operating Region (Upper Limit) */
#define AEB 0x25 /* AGC/AEC - Stable Operating Region (Lower Limit) */
#define VPT 0x26 /* AGC/AEC Fast Mode Operating Region */
#define REG28 0x28 /* Selection on the number of dummy rows, N */
#define HOUTSIZE 0x29 /* Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0]) */
#define EXHCH 0x2A /* Dummy Pixel Insert MSB */
#define EXHCL 0x2B /* Dummy Pixel Insert LSB */
#define VOUTSIZE 0x2C /* Vertical Data Output Size MSBs (LSB at register EXHCH[2]) */
#define ADVFL 0x2D /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */
#define ADVFH 0x2E /* MSB of Insert Dummy Rows in Vertical Sync */
#define YAVE 0x2F /* Y/G Channel Average Value */
#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance High Level Threshold */
#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance Low Level Threshold */
#define HREF 0x32 /* Image Start and Size Control */
#define DM_LNL 0x33 /* Dummy Row Low 8 Bits */
#define DM_LNH 0x34 /* Dummy Row High 8 Bits */
#define ADOFF_B 0x35 /* AD Offset Compensation Value for B Channel */
#define ADOFF_R 0x36 /* AD Offset Compensation Value for R Channel */
#define ADOFF_GB 0x37 /* AD Offset Compensation Value for GB Channel */
#define ADOFF_GR 0x38 /* AD Offset Compensation Value for GR Channel */
#define OFF_B 0x39 /* AD Offset Compensation Value for B Channel */
#define OFF_R 0x3A /* AD Offset Compensation Value for R Channel */
#define OFF_GB 0x3B /* AD Offset Compensation Value for GB Channel */
#define OFF_GR 0x3C /* AD Offset Compensation Value for GR Channel */
#define COM12 0x3D /* DC offset compensation for analog process */
#define COM13 0x3E /* Common Control 13 */
#define COM13_BLC_EN 0x80 /* BLC enable */
#define COM13_ADC_EN 0x40 /* ADC channel BLC ON/OFF control */
#define COM13_ANALOG_BLC 0x20 /* Analog processing channel BLC ON/OFF control */
#define COM13_ABLC_GAIN_EN 0x04 /* ABLC gain trigger enable */
#define COM14 0x3F /* Common Control 14 */
#define COM15 0x40 /* Common Control 15 */
#define COM16 0x41 /* Common Control 16 */
#define TGT_B 0x42 /* BLC Blue Channel Target Value */
#define TGT_R 0x43 /* BLC Red Channel Target Value */
#define TGT_GB 0x44 /* BLC Gb Channel Target Value */
#define TGT_GR 0x45 /* BLC Gr Channel Target Value */
#define LC_CTR 0x46 /* Lens Correction Control */
#define LC_CTR_RGB_COMP_1 0x00 /* R, G, and B channel compensation coefficient is set by LC_COEF (0x49) */
#define LC_CTR_RGB_COMP_3 0x04 /* R, G, and B channel compensation coefficient is set by registers
LC_COEFB (0x4B), LC_COEF (0x49), and LC_COEFR (0x4C), respectively */
#define LC_CTR_EN 0x01 /* Lens correction enable */
#define LC_XC 0x47 /* X Coordinate of Lens Correction Center Relative to Array Center */
#define LC_YC 0x48 /* Y Coordinate of Lens Correction Center Relative to Array Center */
#define LC_COEF 0x49 /* Lens Correction Coefficient */
#define LC_RADI 0x4A /* Lens Correction Radius */
#define LC_COEFB 0x4B /* Lens Correction B Channel Compensation Coefficient */
#define LC_COEFR 0x4C /* Lens Correction R Channel Compensation Coefficient */
#define FIXGAIN 0x4D /* Analog Fix Gain Amplifier */
#define AREF0 0x4E /* Sensor Reference Control */
#define AREF1 0x4F /* Sensor Reference Current Control */
#define AREF2 0x50 /* Analog Reference Control */
#define AREF3 0x51 /* ADC Reference Control */
#define AREF4 0x52 /* ADC Reference Control */
#define AREF5 0x53 /* ADC Reference Control */
#define AREF6 0x54 /* Analog Reference Control */
#define AREF7 0x55 /* Analog Reference Control */
#define UFIX 0x60 /* U Channel Fixed Value Output */
#define VFIX 0x61 /* V Channel Fixed Value Output */
#define AWBB_BLK 0x62 /* AWB Option for Advanced AWB */
#define AWB_CTRL0 0x63 /* AWB Control Byte 0 */
#define AWB_CTRL0_GAIN_EN 0x80 /* AWB gain enable */
#define AWB_CTRL0_CALC_EN 0x40 /* AWB calculate enable */
#define AWB_CTRL0_WBC_MASK 0x0F /* WBC threshold 2 */
#define DSP_CTRL1 0x64 /* DSP Control Byte 1 */
#define DSP_CTRL1_FIFO_EN 0x80 /* FIFO enable/disable selection */
#define DSP_CTRL1_UV_EN 0x40 /* UV adjust function ON/OFF selection */
#define DSP_CTRL1_SDE_EN 0x20 /* SDE enable */
#define DSP_CTRL1_MTRX_EN 0x10 /* Color matrix ON/OFF selection */
#define DSP_CTRL1_INTRP_EN 0x08 /* Interpolation ON/OFF selection */
#define DSP_CTRL1_GAMMA_EN 0x04 /* Gamma function ON/OFF selection */
#define DSP_CTRL1_BLACK_EN 0x02 /* Black defect auto correction ON/OFF */
#define DSP_CTRL1_WHITE_EN 0x01 /* White defect auto correction ON/OFF */
#define DSP_CTRL2 0x65 /* DSP Control Byte 2 */
#define DSP_CTRL2_VDCW_EN 0x08 /* Vertical DCW enable */
#define DSP_CTRL2_HDCW_EN 0x04 /* Horizontal DCW enable */
#define DSP_CTRL2_VZOOM_EN 0x02 /* Vertical zoom out enable */
#define DSP_CTRL2_HZOOM_EN 0x01 /* Horizontal zoom out enable */
#define DSP_CTRL3 0x66 /* DSP Control Byte 3 */
#define DSP_CTRL3_UV_EN 0x80 /* UV output sequence option */
#define DSP_CTRL3_CBAR_EN 0x20 /* DSP color bar ON/OFF selection */
#define DSP_CTRL3_FIFO_EN 0x08 /* FIFO power down ON/OFF selection */
#define DSP_CTRL3_SCAL1_PWDN 0x04 /* Scaling module power down control 1 */
#define DSP_CTRL3_SCAL2_PWDN 0x02 /* Scaling module power down control 2 */
#define DSP_CTRL3_INTRP_PWDN 0x01 /* Interpolation module power down control */
#define DSP_CTRL3_SET_CBAR(r, x) ((r&0xDF)|((x&1)<<5))
#define DSP_CTRL4 0x67 /* DSP Control Byte 4 */
#define DSP_CTRL4_YUV_RGB 0x00 /* Output selection YUV or RGB */
#define DSP_CTRL4_RAW8 0x02 /* Output selection RAW8 */
#define DSP_CTRL4_RAW10 0x03 /* Output selection RAW10 */
#define AWB_BIAS 0x68 /* AWB BLC Level Clip */
#define AWB_CTRL1 0x69 /* AWB Control 1 */
#define AWB_CTRL2 0x6A /* AWB Control 2 */
#define AWB_CTRL3 0x6B /* AWB Control 3 */
#define AWB_CTRL3_ADVANCED 0x80 /* AWB mode select - Advanced AWB */
#define AWB_CTRL3_SIMPLE 0x00 /* AWB mode select - Simple AWB */
#define AWB_CTRL4 0x6C /* AWB Control 4 */
#define AWB_CTRL5 0x6D /* AWB Control 5 */
#define AWB_CTRL6 0x6E /* AWB Control 6 */
#define AWB_CTRL7 0x6F /* AWB Control 7 */
#define AWB_CTRL8 0x70 /* AWB Control 8 */
#define AWB_CTRL9 0x71 /* AWB Control 9 */
#define AWB_CTRL10 0x72 /* AWB Control 10 */
#define AWB_CTRL11 0x73 /* AWB Control 11 */
#define AWB_CTRL12 0x74 /* AWB Control 12 */
#define AWB_CTRL13 0x75 /* AWB Control 13 */
#define AWB_CTRL14 0x76 /* AWB Control 14 */
#define AWB_CTRL15 0x77 /* AWB Control 15 */
#define AWB_CTRL16 0x78 /* AWB Control 16 */
#define AWB_CTRL17 0x79 /* AWB Control 17 */
#define AWB_CTRL18 0x7A /* AWB Control 18 */
#define AWB_CTRL19 0x7B /* AWB Control 19 */
#define AWB_CTRL20 0x7C /* AWB Control 20 */
#define AWB_CTRL21 0x7D /* AWB Control 21 */
#define GAM1 0x7E /* Gamma Curve 1st Segment Input End Point 0x04 Output Value */
#define GAM2 0x7F /* Gamma Curve 2nd Segment Input End Point 0x08 Output Value */
#define GAM3 0x80 /* Gamma Curve 3rd Segment Input End Point 0x10 Output Value */
#define GAM4 0x81 /* Gamma Curve 4th Segment Input End Point 0x20 Output Value */
#define GAM5 0x82 /* Gamma Curve 5th Segment Input End Point 0x28 Output Value */
#define GAM6 0x83 /* Gamma Curve 6th Segment Input End Point 0x30 Output Value */
#define GAM7 0x84 /* Gamma Curve 7th Segment Input End Point 0x38 Output Value */
#define GAM8 0x85 /* Gamma Curve 8th Segment Input End Point 0x40 Output Value */
#define GAM9 0x86 /* Gamma Curve 9th Segment Input End Point 0x48 Output Value */
#define GAM10 0x87 /* Gamma Curve 10th Segment Input End Point 0x50 Output Value */
#define GAM11 0x88 /* Gamma Curve 11th Segment Input End Point 0x60 Output Value */
#define GAM12 0x89 /* Gamma Curve 12th Segment Input End Point 0x70 Output Value */
#define GAM13 0x8A /* Gamma Curve 13th Segment Input End Point 0x90 Output Value */
#define GAM14 0x8B /* Gamma Curve 14th Segment Input End Point 0xB0 Output Value */
#define GAM15 0x8C /* Gamma Curve 15th Segment Input End Point 0xD0 Output Value */
#define SLOP 0x8D /* Gamma Curve Highest Segment Slope */
#define DNSTH 0x8E /* De-noise Threshold */
#define EDGE0 0x8F /* Edge Enhancement Strength Control */
#define EDGE1 0x90 /* Edge Enhancement Threshold Control */
#define DNSOFF 0x91 /* Auto De-noise Threshold Control */
#define EDGE2 0x92 /* Edge Enhancement Strength Upper Limit */
#define EDGE3 0x93 /* Edge Enhancement Strength Upper Limit */
#define MTX1 0x94 /* Matrix Coefficient 1 */
#define MTX2 0x95 /* Matrix Coefficient 2 */
#define MTX3 0x96 /* Matrix Coefficient 3 */
#define MTX4 0x97 /* Matrix Coefficient 4 */
#define MTX5 0x98 /* Matrix Coefficient 5 */
#define MTX6 0x99 /* Matrix Coefficient 6 */
#define MTX_CTRL 0x9A /* Matrix Control */
#define MTX_CTRL_DBL_EN 0x80 /* Matrix double ON/OFF selection */
#define BRIGHTNESS 0x9B /* Brightness Control */
#define CONTRAST 0x9C /* Contrast Gain */
#define UVADJ0 0x9E /* Auto UV Adjust Control 0 */
#define UVADJ1 0x9F /* Auto UV Adjust Control 1 */
#define SCAL0 0xA0 /* DCW Ratio Control */
#define SCAL1 0xA1 /* Horizontal Zoom Out Control */
#define SCAL2 0xA2 /* Vertical Zoom Out Control */
#define FIFODLYM 0xA3 /* FIFO Manual Mode Delay Control */
#define FIFODLYA 0xA4 /* FIFO Auto Mode Delay Control */
#define SDE 0xA6 /* Special Digital Effect Control */
#define SDE_NEGATIVE_EN 0x40 /* Negative image enable */
#define SDE_GRAYSCALE_EN 0x20 /* Gray scale image enable */
#define SDE_V_FIXED_EN 0x10 /* V fixed value enable */
#define SDE_U_FIXED_EN 0x08 /* U fixed value enable */
#define SDE_CONT_BRIGHT_EN 0x04 /* Contrast/Brightness enable */
#define SDE_SATURATION_EN 0x02 /* Saturation enable */
#define SDE_HUE_EN 0x01 /* Hue enable */
#define USAT 0xA7 /* U Component Saturation Gain */
#define VSAT 0xA8 /* V Component Saturation Gain */
#define HUECOS 0xA9 /* Cosine value × 0x80 */
#define HUESIN 0xAA /* Sine value × 0x80 */
#define SIGN_BIT 0xAB /* Sign Bit for Hue and Brightness */
#define DSPAUTO 0xAC /* DSP Auto Function ON/OFF Control */
#define DSPAUTO_AWB_EN 0x80 /* AWB auto threshold control */
#define DSPAUTO_DENOISE_EN 0x40 /* De-noise auto threshold control */
#define DSPAUTO_EDGE_EN 0x20 /* Sharpness (edge enhancement) auto strength control */
#define DSPAUTO_UV_EN 0x10 /* UV adjust auto slope control */
#define DSPAUTO_SCAL0_EN 0x08 /* Auto scaling factor control (register SCAL0 (0xA0)) */
#define DSPAUTO_SCAL1_EN 0x04 /* Auto scaling factor control (registers SCAL1 (0xA1 and SCAL2 (0xA2))*/
#define SET_REG(reg, x) (##reg_DEFAULT|x)
#endif //__REG_REGS_H__