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Nam Tran
2020-10-12 15:38:02 -05:00
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pages/work/gm2/esq/bu_controller.txt Normal file
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{{indexmenu>work:gm2:esq:bu_controller}}

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pages/work/gm2/esq/bu_controller/bu_controller_manual.txt Normal file
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====== Hardware ======
===== Overview =====
The box's job is to emit TTL pulses to control 4 HV pulsers, and stop doing so when a trouble is detected.
===== Block diagram and photo =====
{{work:gm2:esq:bu_controller:bu_controller_block_diagram.png?800x0}}
===== Carrier board =====
The carrier board has a PicoZed System-On-Module (SOM), which contains:
* a XC7Z020 System-on-Chip (one dual core ARM processor, and one Artix-7 FPGA)
* 1 GB of DDR3 SDRAM
* 16 GB eMMC memory
* Ethernet interface
* UART interface
This board serves as a bridge between user and programmable logic parts (ADC boards) of the controller.
There is a Linux system (Xilin Petalinux 2015.4) installed:
* user: ''root''
* password: ''root''
* static IP address: ''192.168.30.89''
===== ADC boards =====
There are 4 identical ADC boards in the box, each has one pulser and one 8-channel waveform digitizer.
{{work:gm2:esq:bu_controller:bu_controller_front_panel.png?800x0}}
==== Pulser ====
{{work:gm2:esq:bu_controller:io_numbering.png?600x0}}
Each pulser has 8 SMA outputs, numbered from 1 to 8 from left to right:
* outputs 1-4: RF control outputs
* output 5: discharge signal
* output 6: charge signal, first step
* output 7: charge signal, second step for two-step HV cabinets. Not used in case of 1-step pulser.
* outputs 8: spare I/O
Pulse modes are:
- External trigger: produces a set of pulse after receiving a LVTTL (3.3 V) logic pulse at the external trigger input. The trigger pulse width should not exceed 50 ns.
- Internal trigger: produces sets of pulses periodically, up to 100 Hz
==== WFD ====
These are 12-bit WFDs, run at 100 MSPS. Clock source can be either an external 40 MHz clock, or internal clock generated by the carrier board.
The WFD inputs are numbered from 1 to 8 from left to right, similar to the pulser numbering above. These inputs have protection against surges might happen during a spark.
The WFDs provide several pieces of information:
* waveforms: all channels are in zero-suppressed mode, which will only export samples above programmed individual threshold. The maximum sampling length is 100 us (the current firmware can only give 20 us)
* spark threshold (not the waveform threshold above) crossings: there are upper and lower thersholds for each channel, the threshold crossing counting is active for the whole g-2 muon fill (~700 us)
* waveform integrals at charge and discharge times: the integration starts at charge and discharge steps, maximum integration length is 256 samples (~2.5 us)
Each WFD will produce one block of data for one trigger, the data format is described here: https://docs.google.com/spreadsheets/d/19r_blWufX368hKRkoa1FGhIzBLOzIvKfg5ZKRVmEVkI/edit?usp=sharing. The data is written to RAM on the carrier board, and can be accessed via a DMA controller.
====== Firmware ======
====== Software ======

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pages/work/gm2/esq/bu_controller/carrier_firmware_2020-10-05_issues.txt Normal file
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* Board 3 could not be initialized
* Skipping every other pulse (yellow) in the 8 pulses train (teal)
{{work:gm2:esq:bu_controller:pxl_20201007_202452451.jpg?400x0}}
* Switching back to ''2019-12-13'' version fixed both of them
{{work:gm2:esq:bu_controller:pxl_20201007_210215108.jpg?400x0}}

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pages/work/gm2/esq/bu_controller/carrier_firmware_2020-10-08_test.txt Normal file
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====== First test ======
* It seems the issue of board initialization is still there, but moves to board 4 ...
* Still shows only 4 out of 8 pulses in a train
* will try with different triggers
<code bash>
daq@gm2-01:scripts $ BUTool -q 192.168.30.89
Registered device: G2QUAD
>write TRIGGER.STATUS.ENABLE_PULSERS 1
Write to register TRIGGER.STATUS.ENABLE_PULSERS
>write TRIGGER.FREE_RUN.EN_FR_TRIG 0
Write to register TRIGGER.FREE_RUN.EN_FR_TRIG
>write TRIGGER.FREE_RUN.EN_EXT_TRIG 1
Write to register TRIGGER.FREE_RUN.EN_EXT_TRIG
>read SYSTEM.SYNTH_DATE
SYSTEM.SYNTH_DATE: 0x20201008
>read ADCBOARD.1.*SYNTH_DATE
ADCBOARD.1.SYSTEM.SYNTH_DATE: 0x20201005
>read ADCBOARD.2.*SYNTH_DATE
ADCBOARD.2.SYSTEM.SYNTH_DATE: 0x20201005
>read ADCBOARD.3.*SYNTH_DATE
ADCBOARD.3.SYSTEM.SYNTH_DATE: 0x20201005
</code>
====== Trigger from a waveform generator ======
* The function generator is programmed to output a burst of 8 pulses: 3 Vpp, 1.5 V offset, 10 ms separation every 1.4 s. Pulse width is adjustable. This WG has minimum 6 ns rise time and fall time.
{{work:gm2:esq:bu_controller:pxl_20201008_190541385.jpg?600x0}}
* Output 1 & 2 are in-sync
{{work:gm2:esq:bu_controller:pxl_20201008_190526636.jpg?600x0}}
* Output 1 is kept on channel 1 of the scope, output 2 goes to the ext. trigger input of the BU controller
====== Tweaking trigger pulse length ======
Channel 1 on scope is the synced signal of ext trigger, channel 2 is discharge pulse from ADC board 1.
* < 50 ns, still shows only 4 pulses. All pulses from 12 ns to 50 ns worked.
{{work:gm2:esq:bu_controller:pxl_20201008_191532389.jpg}}
{{work:gm2:esq:bu_controller:pxl_20201008_191547871.jpg}}
{{work:gm2:esq:bu_controller:pxl_20201008_191643263.jpg}}
{{work:gm2:esq:bu_controller:pxl_20201008_191710289.jpg}}
{{work:gm2:esq:bu_controller:pxl_20201008_191730525.jpg}}
* 54 ns, picking up random pulses among 8, but never 2 consecutive ones
{{work:gm2:esq:bu_controller:pxl_20201008_191758570.jpg}}
{{work:gm2:esq:bu_controller:pxl_20201008_191806670.jpg}}
{{work:gm2:esq:bu_controller:pxl_20201008_191757168.jpg}}
* 56 ns, still can pick up pulses
{{work:gm2:esq:bu_controller:pxl_20201008_191818632.jpg}}
{{work:gm2:esq:bu_controller:pxl_20201008_191821833.jpg}}
* 60 ns, no trigger picked up at all
===== Different pulse separation =====
Still only 4 pulses, there seems to be some change in phase.
{{work:gm2:esq:bu_controller:pxl_20201008_195535792.jpg}}{{work:gm2:esq:bu_controller:pxl_20201008_195613934.jpg}}{{work:gm2:esq:bu_controller:pxl_20201008_195009724.jpg}}{{work:gm2:esq:bu_controller:pxl_20201008_194714818.jpg}}

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pages/work/gm2/esq/bu_controller/compiling_on_gm2-01.txt Normal file
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====== Prepare code ======
===== Zynq software =====
<code bash>
daq@gm2-01:ESQ $ svn co http://gauss.bu.edu/svn/g2-quad-pulser.firmware/carrier zynq-carrier.trunk.svn
...
Checked out revision 548.
daq@gm2-01:zynq-carrier.trunk.svn $ svn log | head
------------------------------------------------------------------------
r548 | dgastler | 2020-10-05 15:11:09 -0500 (Mon, 05 Oct 2020) | 1 line
New version for Nam
------------------------------------------------------------------------
r546 | dgastler | 2020-10-05 07:52:45 -0500 (Mon, 05 Oct 2020) | 1 line
updated address tables
------------------------------------------------------------------------
r545 | dgastler | 2020-10-05 07:17:03 -0500 (Mon, 05 Oct 2020) | 1 line
</code>
===== Copy old BUTool over =====
<code bash>
daq@gm2-01:zynq-carrier.trunk.svn $ cp -r ~/ESQ/zynq-carrier.trunk/os/software/BUTool ./os/software/
</code>
====== Build ======
===== BUTool =====
Clean up old code, regenerate ''env.sh'', then ''make'' again
<code bash>
daq@gm2-01:BUTool $ export PLATFORM=petalinux
daq@gm2-01:BUTool $ ./setup.sh
env.sh
Source env.sh and run 'make' to build BUTool
daq@gm2-01:BUTool $ make clean
daq@gm2-01:BUTool $ make -j4 && make install
</code>
===== Zynq software =====
Edit the ''buildArm.sh'' a little bit (skip building BUTool since it is done in previous step)
<code bash>
daq@gm2-01:software $ ./buildArm.sh
</code>

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====== Check out codes ======
===== Zynq software =====
<code bash>
nam@opt:ESQ $ svn co http://gauss.bu.edu/svn/g2-quad-pulser.firmware
nam@opt:ESQ $ mv g2-quad-pulser.firmware g2-quad-pulser.firmware.svn
nam@opt:g2-quad-pulser.firmware.svn $ cd carrier/trunk/os/software/
</code>
Make sure this is the latest version (as of 2020/10/05):
<code>
nam@opt:software $ svn info
Path: .
Working Copy Root Path: /home/nam/work/gm2/ESQ/g2-quad-pulser.firmware.svn
URL: http://gauss.bu.edu/svn/g2-quad-pulser.firmware/carrier/trunk/os/software
Relative URL: ^/carrier/trunk/os/software
Repository Root: http://gauss.bu.edu/svn/g2-quad-pulser.firmware
Repository UUID: 7ce3f3ac-83d5-4068-a32b-ab773f4188fc
Revision: 548
Node Kind: directory
Schedule: normal
Last Changed Author: dgastler
Last Changed Rev: 546
Last Changed Date: 2020-10-05 07:52:45 -0500 (Mon, 05 Oct 2020)
</code>
===== BUTool =====
<code bash>
nam@opt:software $ svn co http://gauss.bu.edu/svn/butool/trunk BUTool
nam@opt:BUTool $ svn info
...
Last Changed Rev: 70
Last Changed Date: 2019-09-17 10:35:07 -0500 (Tue, 17 Sep 2019)
</code>
Need to revert to ''r42'' which is compatible with Petalinux 2015.4
<code bash>
nam@opt:BUTool $ svn up -r42
nam@opt:BUTool $ svn info
Path: .
Working Copy Root Path: /home/nam/work/gm2/ESQ/g2-quad-pulser.firmware.svn/carrier/trunk/os/software/BUTool
URL: http://gauss.bu.edu/svn/butool/trunk
...
Last Changed Rev: 42
Last Changed Date: 2018-07-12 15:56:11 -0500 (Thu, 12 Jul 2018)
</code>
====== Build ======
===== BUTool =====
Run ''setup.sh'' to generate ''env.sh'' where all environment variables would be set. Also change the path to Petalinux to match the local installation.
<code bash>
nam@opt:BUTool $ PLATFORM=petalinux ./setup.sh
env.sh
Source env.sh and run 'make' to build BUTool
nam@opt:BUTool $ cat env.sh
if [[ $_ == $0 ]]; then
echo "$0 is meant to be sourced:"
echo " source $0"
exit 0
fi
export PLATFORM="petalinux"
export PREFIX="/work/butool"
export MAKEFLAGS="-I /home/nam/work/gm2/ESQ/g2-quad-pulser.firmware.svn/carrier/trunk/os/software/BUTool/mk"
export PROJECT_ROOT="/home/nam/work/gm2/ESQ/g2-quad-pulser.firmware.svn/carrier/trunk/os/software/BUTool"
export PATH="$PATH:/work/butool/bin"
export VIVADO_VERSION=2015.4
export VIVADO_SDK=/home/nam/Downloads/petalinux-v2015.4-final/settings.sh
source $VIVADO_SDK
export CXX=arm-xilinx-linux-gnueabi-g++
export CC=arm-xilinx-linux-gnueabi-gcc
export CROSS_HOST=arm-xilinx-linux-gnueabi
export MAKEOBJDIRPREFIX="$PROJECT_ROOT/obj"
export DESTDIR="$PROJECT_ROOT/install"
export BUTOOL_COMPILETIME_PATH="$DESTDIR/$PREFIX"
export BUTOOL_RUNTIME_PATH="$PREFIX"
</code>
Source ''env.sh'' and ''make'':
<code bash>
nam@opt:BUTool $ . env.sh
nam@opt:BUTool $ make
...
CXX (link) -o obj/lib/libBUTool.so
CXX src/tool/BUTool.cxx
CXX (link) -o obj/bin/BUTool
</code>
===== Zynq software =====
<code bash>
nam@opt:BUTool $ cd ../
nam@opt:software $ ./buildArm.sh
</code>
Need to change a few things
<code bash>
nam@opt:software $ svn diff
Index: buildArm.sh
===================================================================
--- buildArm.sh (revision 548)
+++ buildArm.sh (working copy)
@@ -15,7 +15,7 @@
export PLATFORM=petalinux
cd BUTool
-./setup.sh
+#./setup.sh
source env.sh
make clean
make
Index: zynq_daq/Makefile
===================================================================
--- zynq_daq/Makefile (revision 548)
+++ zynq_daq/Makefile (working copy)
@@ -1,6 +1,9 @@
+SHELL := /bin/bash
VIVADO_VERSION=2015.4
#VIVADO_VERSION=2017.2
VIVADO_SDK="/opt/Xilinx/SDK/"${VIVADO_VERSION}"/settings64.sh"
+VIVADO_SDK=/home/nam/Downloads/petalinux-v2015.4-final/settings.sh
+
CXX=source ${VIVADO_SDK} && arm-xilinx-linux-gnueabi-g++
#CXXFLAGS+=-c -g -O2 -Wall -Wextra -Werror -Wno-pointer-arith -I ./ -I ${G2FRAME_PREFIX}/include
Index: zynq_pl_bridge/Makefile
===================================================================
--- zynq_pl_bridge/Makefile (revision 548)
+++ zynq_pl_bridge/Makefile (working copy)
@@ -1,6 +1,7 @@
VIVADO_VERSION=2015.4
VIVADO_SDK="/opt/Xilinx/SDK/"$(VIVADO_VERSION)"/settings64.sh"
+VIVADO_SDK=/home/nam/Downloads/petalinux-v2015.4-final/settings.sh
CXX=source $(VIVADO_SDK) && arm-xilinx-linux-gnueabi-g++
CXXFLAGS+=-c -O2 -static -Wall -Wextra -Werror -Wno-pointer-arith
</code>

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pages/work/gm2/esq/bu_controller/test_with_single_burst_of_8_pulses.txt Normal file
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- log-01: before
- log-02: after
- log-03: another pulse